Results 261 to 270 of about 9,214 (294)

Temperature-aware wireless network-on-chip architecture

International Green Computing Conference, 2014
Long-range wireless shortcuts in Network-on-Chip (NoC) architectures are shown to significantly improve energy-efficiency in on-chip data transfer. However, over-utilization of the wireless shortcuts and non-uniform traffic patterns may result in thermal hotpots in the NoC links or switches.
Md Shahriar Shamim, Aniket Mhatre, Naseef Mansoor, Amlan Ganguly, Gill R. Tsouri   +4 more
openaire   +1 more source

A Generic On-Chip Debugger for Wireless Sensor Networks

First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06), 2006
This invited paper overviews the low level debug support hardware required for an on-chip pre-deployment debugging system for sensor networks. The solution provides significant program and data trace compression using a low complexity messaging framework. The architecture targets system-on-chip designs with multiple processor cores.
Andrew B. T. Hopkins, Klaus D. McDonald-Maier   +1 more
openaire   +1 more source

Performance evaluation of wireless networks on chip architectures

2009 10th International Symposium on Quality of Electronic Design, 2009
The performance benefits of conventional Network-on-Chip (NoC) architectures are limited by the high latency and energy dissipation in long distance multihop communication between embedded cores. To alleviate these problems, wireless on-chip networks are envisioned.
Amlan Ganguly, Kevin Chang 0002, Partha Pratim Pande, Benjamin Belzer, Alireza Nojeh   +4 more
openaire   +1 more source

Flow Control Mechanism for Wireless Network-on-Chip

2013 10th International Conference on Information Technology: New Generations, 2013
Network on chip (NoC) provides a network-based interconnect infrastructure that facilitates the communications among a slew of function cores in a modern System-on-chip (SoC) design. Apart from topology, switching technique and routing strategy adopted in an NoC, flow control scheme that regulates the packet injection rates is another determining ...
Ling Wang 0004, Zhen Wang, Yingtao Jiang
openaire   +1 more source

Toward THz RIS-Parametrized Wireless Networks-on-Chip

Proceedings of the 10th ACM International Conference on Nanoscale Computing and Communication, 2023
Wireless networks-on-chip (WNoCs) are a promising complementary interconnect technology to overcome the communication bottleneck of many-core chips. Yet, pecularities of the on-chip radio environment like its strong reverberation still thwart WNoCs.
Jean Tapie, Mohammadreza F. Imani, Philipp del Hougne   +2 more
openaire   +2 more sources

A novel hierarchical architecture for Wireless Network-on-Chip

Journal of Parallel and Distributed Computing, 2018
Abstract In the architecture of Networks-on-Chip (NoCs), wired structure and multi-hop communications can lead to high power consumption and latency. Wireless NoC (WiNoC) architecture is a new alternative to solve these challenges. In this architecture, long-range wireless links are used instead of multi-hop wired paths.
Bahareh Bahrami, Mohammad Ali Jabraeil Jamali, Shahram Saeidi   +2 more
openaire   +1 more source

Antennas and Channel Characteristics for Wireless Networks on Chips

Wireless Personal Communications, 2017
We review the current state of the art on antennas for use in wireless networks on chips (WiNoCs) and also provide results on wireless channel characteristics in the WiNoC setting—the latter are largely absent from the literature. We first describe the motivation for constructing these miniature networks, aimed at improving efficiency of future multi ...
William Rayess, David W. Matolak, Savas Kaya, Avinash Karanth Kodi   +3 more
openaire   +1 more source

Energy Efficient Transceiver in Wireless Network on Chip Architectures

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016
The emergent wireless Network-on-Chip (WiNoC) design paradigm has been proposed as a viable solution for addressing the scalability issues affecting the on-chip communication system in future manycores architectures. Within this scenario, the energy contribution of the buffers (both of the routers and radio-hubs) and the transceivers of the radio-hubs,
CATANIA, Vincenzo, Mineo A., MONTELEONE, SALVATORE, PALESI, MAURIZIO, PATTI, DAVIDE   +4 more
openaire   +3 more sources

Hybrid wireless Network on Chip

Proceedings of the 2nd International Workshop on Network on Chip Architectures, 2009
The performance benefits of conventional Network-on-Chip (NoC) architectures are limited by the high latency and energy dissipation in long distance multihop communication between embedded cores. This limitation of conventional NoC architectures can be addressed by introducing long-range, high bandwidth and low power wireless links between the distant ...
Partha Pratim Pande, Amlan Ganguly, Kevin Chang 0002, Christof Teuscher   +3 more
openaire   +1 more source

Complex network-enabled robust wireless network-on-chip architectures

ACM Journal on Emerging Technologies in Computing Systems, 2013
The Network-on-Chip (NoC) paradigm has emerged as a scalable interconnection infrastructure for modern multicore chips. However, with growing levels of integration, the traditional NoCs suffer from high latency and energy dissipation in on-chip data transfer due to conventional multihop metal/dielectric-based interconnects.
Paul Wettin, Anuroop Vidapalapati, Amlan Ganguly, Partha Pratim Pande   +3 more
openaire   +1 more source