Results 271 to 280 of about 9,214 (294)

Wireless network-on-chip: a new era in multi-core chip design

2014 25nd IEEE International Symposium on Rapid System Prototyping, 2014
The Network-on-Chip (NoC) is an enabling technology to integrate large numbers of embedded cores on a single die. The existing method of implementing a NoC with planar metal interconnects is deficient due to high latency and significant power consumption arising out of multi-hop links used in data exchange.
Sujay Deb, Hemanta Kumar Mondal
openaire   +1 more source

A New Frontier in Ultralow Power Wireless Links: Network-on-Chip and Chip-to-Chip Interconnects

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015
This paper explores the general framework and prospects for on-chip and off-chip wireless interconnects implemented for high-performance computing (HPC) systems in the context of micro power wireless design. HPC interconnects demand very high (≥ 10 Gb/s) transmission rates using ultraefficient ( $\sim ~1$ pJ/bit) transceivers over extremely short (
Laha, Soumyasanta, Kaya, Savas, Matolak, David W, Rayess, William, DiTomaso, Dominic, Kodi, Avinash   +5 more
openaire   +2 more sources

An Exploration on Quantity and Layout of Wireless Nodes for Hybrid Wireless Network-on-Chip

2014 IEEE Intl Conf on High Performance Computing and Communications, 2014 IEEE 6th Intl Symp on Cyberspace Safety and Security, 2014 IEEE 11th Intl Conf on Embedded Software and Syst (HPCC,CSS,ICESS), 2014
As the scaling of integration, massive remote communication has become the main bottleneck of system performance for network-on-chip (NoC). Most packets have to travel long distances from source to destination, leading to long latency and severe contention. Hybrid Wireless NoC(HWiNoC) has emerged as a popular method to handle remote transmission in NoC,
Mingmin Yuan, Weiwei Fu, Tianzhou Chen, Minghui Wu 0001   +3 more
openaire   +1 more source

A Statistical Model for Hybrid Wireless Network on Chip

2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), 2016
A scalable and easy to design solution for the continuing demand of high performance chip multiprocessors paved the way for Hybrid Wireless Network on Chip (WiNoC) architectures which comprises of both wired and wireless channel interconnects for communication.
openaire   +1 more source

Design and Implementation of Routing Scheme for Wireless Network-on-Chip

2007 IEEE International Symposium on Circuits and Systems, 2007
Modern embedded SoC design uses a rapidly increasing number of processing units for ubiquitous computing. When moving towards a billion-transistor era, ever increasing complexity, density and heterogeneity of embedded components exacerbate on-chip communication, which serves as the fabric to integrate these components and provide a communication ...
Yi Wang 0007, Dan Zhao 0001
openaire   +1 more source

An implementation of security mechanism in chip for industrial wireless networks

2017 International Conference on Information Networking (ICOIN), 2017
Security and real-time communication becomes more and more important for the widely application of industrial wireless technology in industrial system. However, it is difficult to guarantee both security and the real-time performance at same time in deterministic industrial wireless networks.
Min Wei, Zhen Wang, Keecheon Kim
openaire   +1 more source

Energy efficient modulation for a wireless network-on-chip architecture

10th IEEE International NEWCAS Conference, 2012
As both power consumption and leakage currents will limit the scalability of future massively integrated computational systems, research into emerging technologies and devices to replace traditional metallic interconnects has become critical. In this paper we propose an initial implementation for a hybrid wireless network-on-chip (WiNoC) interconnect ...
Dominic DiTomaso, Soumyasanta Laha, Savas Kaya, David W. Matolak, Avinash Kodi   +4 more
openaire   +1 more source

LAWI: A load balanced architecture for wireless network on chip

2016 International Conference on Advances in Computing, Communications and Informatics (ICACCI), 2016
The advancement in the designing of multicores system-on-chip pose the requirement of communication infrastructure which provides target performance to meet the computation requirement of gigascale processors. Thus a promising solution called LAWI, a Load balanced Architecture for Wireless Network on chip, has been proposed to bridge the widening gap ...
openaire   +1 more source

Challenges and opportunities of wireless network-on-chip for manycore architectures

Proceedings of the 12th International Workshop on Network on Chip Architectures, 2019
Increasing core count heralds the arrival of massive shared-memory chip multiprocessors. For such a scenario, traditional on-chip networks have been proven to not scale well neither in terms of transmission latency nor in terms of energy consumption. The Wireless Network-on-Chip (WNoC) paradigm holds considerable promise for the implementation of fast ...
openaire   +1 more source

A survey and taxonomy of congestion control mechanisms in wireless network on chip

Journal of Systems Architecture, 2020
Midia Reshadi, Ahmad Khademzadeh
exaly