Results 191 to 200 of about 73,895 (232)
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Vertical-channel stacked array (VCSTAR) for 3D NAND flash memory
2011 International Semiconductor Device Research Symposium (ISDRS), 2011Abstract A novel three-dimensional (3D) NAND flash memory, VCSTAR (Vertical-Channel STacked ARray), is investigated. The proposed device is a vertical channel structure having stacked word-lines to achieve high memory density without shrinking cell channel length.
Se Hwan Park +4 more
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Characterization of Inter-Cell Interference in 3D NAND Flash Memory
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021We characterize inter-cell interference in commercial three-dimensional NAND flash memory. By writing random data into 3D NAND and collecting sample means and sample variances of cell values corresponding to a particular set of input values in fixed relative neighboring cell locations, it is shown that the interference coming from any target cell ...
Suk Kwang Park, Jaekyun Moon
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Overview of Advanced 3D Charge-trapping Flash Memory Devices
MRS Proceedings, 2010AbstractAlthough conventional floating gate (FG) Flash memory has already gone into the sub-30 nm node, the technology challenges are formidable beyond 20nm. The fundamental challenges include FG interference, few-electron storage caused statistical fluctuation, poor short-channel effect, WL-WL breakdown, poor reliability, and edge effect sensitivity ...
Hang-Ting Lue +2 more
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3D Flash Memory for Data-Intensive Applications
2018 IEEE International Memory Workshop (IMW), 2018In this review paper, the advantages in latest 3D Flash memory are discussed from the viewpoints of Scalability, Reliability, and Efficiency for the Data-intensive applications. By a lot of recent improvements in fabrication process and circuit design, 3D Flash memory offers unique solution for future high-performance data storage.
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3D VG-Type NAND Flash Memories
2016The common feature among the different 3D NAND solutions is constituted by very deep vertical (z direction) etching steps that define the Flash cells geometries simultaneously. Transistor geometries are formed by the deep trench through a multiple polysilicon/oxide stack.
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Study on cell shape in 3D NAND flash memory
2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), 2015All kinds of cell structures are appeared in 3D NAND flash technologies and all seem to be promising. In this paper, detail comparisons among the cell structures of them are presented. The theoretical derivation and simulation results both support that the cylindrical cell structure has better program/erase speed and memory window.
Wei Feng, Nine Deng
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Optimization of Performance and Reliability in 3D NAND Flash Memory
IEEE Electron Device Letters, 20203D NAND Flash with high storage capacity is in great demand for several technologies, which requires high performance and good reliability at the same time. Therefore, it is proposed to adjust the tunnel layer by changing the first SiO2 (O1) layer thickness near poly Si channel in the tunnel layer based on SiO2/SiOxNy/SiO2 structure.
Yingjie Ouyang +5 more
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Error Generation for 3D NAND Flash Memory
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022Weihua Liu +4 more
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Multilevel In-Memory-Searching in 3D NAND-Flash Memory
Extended Abstracts of the 2022 International Conference on Solid State Devices and Materials, 2022Po Hao Tseng +9 more
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