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Design of power efficient All Digital Phase Locked Loop (ADPLL)
2016 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), 2016This paper presents a power efficient design of All Digital Phase Locked Loop (ADPLL). The proposed ADPLL uses power optimized digital loop filter instead of the conventional one. The power optimization of digital loop filter is carried out with the aid of clock gating technique without degrading the performance of the overall system.
Nitesh Tripathi, Sambhu Nath Pradhan
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A noval fast-locking ADPLL based on Newton's Method
2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC), 2018Based on the idea of Newton's Method, a new structure of AllDigital Phased-Locked Loop(ADPLL) is proposed. The ADPLL is made up of a fully customized frequency comparator, controller and digital-controlled oscillator (DCO). The proposed structure and locking method are different from the traditional one. RTL simulation results show that the lockin time
Xiaoying Deng +2 more
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A Sigma-Delta Fractional-N Frequency Synthesizer Based on ADPLL
2010 International Conference on Intelligent Computation Technology and Automation, 2010in this paper, we propose a fractional-N frequency synthesizer based on All Digital Phase Locked Loop (ADPLL). We use phase-frequency detector as PD, up/down counter as LF, P-Divider counter as DCO, and the dual-modulus N/N+1 divider is controlled by the output of the sigma-delta modulation to achieve the goal of spur reduction.
Wei Sun, Hexiang Wen, Lizhong Gao
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Efficient Modeling and Simulation of Accumulator-Based ADPLLs
2013In this chapter, we focus on the behavioral modeling and simulation of accumulator-based ADPLLs. First, we introduce some basic concepts related to mixed-signal systems and simulators. We highlight the major issues for the simulation of an ADPLL as an example mixed-signal system.
Francesco Brandonisio +1 more
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Synthesizable ADPLL Generator: From Specification to GDS
2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2023Kyumin Kwon, David D. Wentzloff
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A Broadband ADPLL Design with Automatic Mode Change
2022 7th International Conference on Integrated Circuits and Microsystems (ICICM), 2022Zhen Shen, Xin-Hao Xu, Cheng Liu
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A 1.6–880MHz synthesizable ADPLL in 0.13um CMOS
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2008null Hsiang-Hui Chang +4 more
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An ADPLL Design Model Based on LoRa IoT Application
2023 IEEE 15th International Conference on ASIC (ASICON), 2023Yiyun Mao +4 more
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