DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW [PDF]
Jurnal Teknologi, 2019 Digital controlled oscillator (DCO) is becoming an attractive replacement over the voltage control oscillator (VCO) with the advances of digital intensive research on all-digital phase locked-loop (ADPLL) in complementary metal-oxide semiconductor (CMOS) process technology.
Choong, Florence +6 more
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A Novel Architecture of ADPLL Using Cordic Algorithm for Low-Frequency Application [PDF]
, 2023 All Digital Phase Locked Loop (ADPLL) has many applications in digital communication. It is difficult for low-frequency applications to achieve the lock state quickly.
Velamarthi Spandana,, et al.
core +2 more sources
ALL-DIGITAL PHASE LOCKED LOOP (ADPLL) TOPOLOGIES FOR RFID SYSTEM APPLICATION: A REVIEW
Jurnal Teknologi, 2021 An all-digital phase locked loop (ADPLL)-based local oscillator (LO) of RF transceiver application such as radio-frequency identification (RFID) system has gained popularity by accessing the benefits in complementary metal-oxide semiconductor (CMOS) process technology.
S. N. Ishak +3 more
openaire +3 more sources
An analysis of ADPLL applications in various fields [PDF]
, 2020 ADPLL is now an essential component in applications like wireless sensor networks, Internet of things, health care applications, agricultural applications, etc, and also due the requirement of digital implementation by the industries. ADPLL consists of a
Dinesh, R., Marimuthu, Ramalatha
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Design of a 3 GHz fine resolution LC DCO [PDF]
, 2017 In this thesis, the design of a fine resolution LC digitally controlled oscillator (DCO) is introduced. Two NMOS varactor banks are used to achieve 12 bits medium and fine frequency tuning.
Zhao, Xuming, active 21st century
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Design and VHDL Modeling of All-Digital PLLs [PDF]
, 2010 International audienceIn this paper, a VHDL model of a second-order alldigital phase-locked loop (ADPLL) based on bang-bang phase detectors is presented.
Anceau, François +5 more
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A clock network of distributed ADPLLs using an asymmetric comparison strategy [PDF]
, 2010 International audienceIn this paper, we describe an architecture of a distributed ADPLL (All Digital Phase Lock Loop) network based on bang-bang phase detectors that are interconnected asymmetrically.
Blanco, Eric +5 more
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A Design Approach for Networks of Self-Sampled All-Digital Phase-Locked Loops [PDF]
, 2011 International audienceThis paper addresses the problem of the stability and the performance analysis of N-nodes Cartesian networks of self-sampled all digital phase-locked loops.
Akré, Jean-Michel +6 more
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FPGA implementation of reconfigurable ADPLL network for distributed clock generation [PDF]
, 2011 International audienceThis paper presents an FPGA platform for the design and study of network of coupled All-Digital Phase Locked Loops (ADPLLs), destined for clock generation in large synchronous System on Chip (SoC).
Anceau, François +9 more
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Design of a compact and low-power TDC for an array of SiPM's in 110nm CIS technology [PDF]
, 2017 Silicon photomultipliers (SiPMs) are meant to substitute photomultiplier tubes in high-energy physics detectors and nuclear medicine. This is because of their -to name a few interesting properties- compactness, lower bias voltage, tolerance to magnetic ...
Bandi, Franco +3 more
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