Results 91 to 100 of about 568 (122)
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Capacitive Boosted Ring Oscillators for All-Digital Phase-Locked Loops (ADPLLs)
Journal of Circuits, Systems and Computers, 2021Ring oscillator (RO)-based digital phase-locked loops (DPLLs) are very attractive for system-on-chip applications due to their tuning range, good phase noise property but suffer from compactness and power requirements. In this work, the concept of capacitive boosting as one of the key solutions which enhances the amplitude of oscillations of the RO is
Vikas Balikai, Harish Kittur
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A CMOS implementation of controller based all digital phase locked loop (ADPLL)
Circuit World, 2020Purpose Biomedical radio frequency (RF) transceivers require miniaturized forms with long battery life and low power consumption. The medical implant communication service (MICS) band in the frequency range of 402–405 MHz is widely used for medical RF transceivers because the MICS band signals have reasonable propagation characteristics and are suited
Vikas Balikai, Harish Kittur
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Design of power efficient All Digital Phase Locked Loop (ADPLL)
2016 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), 2016This paper presents a power efficient design of All Digital Phase Locked Loop (ADPLL). The proposed ADPLL uses power optimized digital loop filter instead of the conventional one. The power optimization of digital loop filter is carried out with the aid of clock gating technique without degrading the performance of the overall system.
Nitesh Tripathi, Sambhu Nath Pradhan
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An all-digital phase-locked loop (ADPLL)-based clock recovery circuit
IEEE Journal of Solid-State Circuits, 1999A new algorithm for all-digital phase-locked loops (ADPLL) with fast acquisition and large pulling range is presented in this paper. Based on the proposed algorithm, portable cell-based implementations for clock recovery with functions of a frequency synthesizer and on-chip clock generator are completed by standard cell.
null Terng-Yin Hsu +2 more
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Single-Event Characterization of Bang-bang All-digital Phase-locked Loops (ADPLLs)
IEEE Transactions on Nuclear Science, 2015The single-event vulnerability of a bang-bang ADPLL is investigated through fault injection experiments and circuit simulations. Single-event upsets in the digital loop filter result in the worst-case error response of the ADPLL, often requiring phase reacquisition.
Y. P. Chen +7 more
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Design and simulation of FPGA based all digital phase locked loop (ADPLL)
2017 3rd International Conference on Applied and Theoretical Computing and Communication Technology (iCATccT), 2017Phase locked loops are most widely used in communication systems. Most of the PLL's that are used currently are hybrid type PLL's, where only the phase detectors are digital where as voltage controlled oscillators and loop filters are analog. This article presents an all digital approach for the design, simulation, Synthesis, and implementation of FPGA
Shruti Edway, R K Manjunath
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All-Digital Phase Locked Loop (ADPLL) with an up-down counter using Simulink
2017 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), 2017The concept of an All Digital Phase Locked Loop (ADPLL) with an up-down counter is conceived and presented here. The phase error of a Phase Detector (PD) in a Digital PLL is delivered in bits. The proposed structure enlists an Up-Down Counter to convert this phase error into a suitable input for the Digitally Controlled Oscillator (DCO).
V. Vaithianathan +3 more
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Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558), 2002
In this paper a new architecture for all digital phase locked loop (ADPLL) is proposed The new architecture is based on the ADPLL architecture proposed by Motorola in 1995 but modified in some block A new binary search decision scheme was used to accelerate the frequency acquisition process.
null Kuo-Hsing Cheng, null Yu-Jung Chen
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In this paper a new architecture for all digital phase locked loop (ADPLL) is proposed The new architecture is based on the ADPLL architecture proposed by Motorola in 1995 but modified in some block A new binary search decision scheme was used to accelerate the frequency acquisition process.
null Kuo-Hsing Cheng, null Yu-Jung Chen
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RTL & Physical Design Flow of Power Efficient Components of All Digital Phase Locked Loop (ADPLL)
2022 IEEE International Conference on Nanoelectronics, Nanophotonics, Nanomaterials, Nanobioscience & Nanotechnology (5NANO), 2022Aaditya Joshi +2 more
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All Digital Phase Locked Loop (ADPLL) and Its Blocks—A Comprehensive Knowledge
2022Lalita Yadav, Manoj Duhan
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