Results 11 to 20 of about 568 (122)
An Interpolated Flying‐Adder‐Based Frequency Synthesizer
Journal of Electrical and Computer Engineering, Volume 2011, Issue 1, 2011., 2011 This work presents an interpolated flying‐adder‐ (FA‐) based frequency synthesizer. The architecture of an interpolated FA, which uses an interpolated multiplexer (MUX) to replace the multiplexer in conventional flying adder, improves the cycle‐to‐cycle jitter and root‐mean‐square (RMS) jitter performance.
Pao-Lung Chen +2 more
wiley +2 more sources
Parallel PWMs based fully digital transmitter with wide carrier frequency range. [PDF]
ScientificWorldJournal, 2013 The carrier‐frequency (CF) and intermediate‐frequency (IF) pulse‐width modulators (PWMs) based on delay lines are proposed, where baseband signals are conveyed by both positions and pulse widths or densities of the carrier clock. By combining IF‐PWM and precorrected CF‐PWM, a fully digital transmitter with unit‐delay autocalibration is implemented in ...
Zhou B, Zhang K, Zhou W, Zhang Y, Liu D.
europepmc +2 more sources
An ADPLL-Based GFSK Modulator with Two-Point Modulation for IoT Applications. [PDF]
Sensors (Basel)To establish ubiquitous and energy-efficient wireless sensor networks (WSNs), short-range Internet of Things (IoT) devices require Bluetooth low energy (BLE) technology, which functions at 2.4 GHz. This study presents a novel approach as follows: a fully
Kim NS.
europepmc +2 more sources
IEEE Access, 2021 This paper presents a 0.46 mW and 2.4 GHz; All-Digital Phase-Locked Loop (ADPLL) through an Injection-Locked Frequency Multiplier (ILFM) and Continuous Frequency Tracking Loop (CFTL) circuitry for low power Internet-of-Thing (IoT) applications.
Muhammad Riaz Ur Rehman +14 more
doaj +1 more source
A Fast-Locking All-Digital PLL With Triple-Stage Phase-Shifting
IEEE Access, 2021 This presents an all-digital phase-locked loop (ADPLL) system using triple-stage phase-shifting (TSPS) for fast locking. At the first stage, a phase-pulling multiplexer linearly pulls the phase of a feedback signal until the phase offset between the ...
Heon Hwa Cheong, Suhwan Kim
doaj +1 more source
Design of a high‐performance advanced phase locked loop with high stability external loop filter
IET Circuits, Devices &Systems, Volume 17, Issue 1, Page 1-12, January 2023., 2023 Abstract For this task, an improved phase locked loop (PLL) was developed using a more sophisticated phase‐frequency detector with multiband flexible dividers that provide enhanced frequency resolution, a better spectrum, and a better output signal. Great timing jitter was the problem for the old PLL designs because of the unbalanced frequency transfer
Kalpana Kasilingam +3 more
wiley +1 more source
A 190.3‐dBc/Hz FoM 16‐GHz rotary travelling‐wave oscillator with reliable direction control
Electronics Letters, Volume 57, Issue 5, Page 209-211, March 2021., 2021 Abstract This letter presents a rotary travelling‐wave oscillator (RTWO) with reliable direction control in a standard 130 nm complementary metal–oxide–semiconductor (CMOS) technology. To achieve low phase noise (PN), and low power consumption, 16‐stages customised transmission line segments are designed and simulated on electromagnetic tools.
Fangzhou Sun +3 more
wiley +1 more source
FPGA implantations of TRNG architecture using ADPLL based on FIR filter as a loop filter
SN Applied Sciences, 2022 This article describes about the design, implementation, and analysis of a true random number generator (TRNG) employing an all-digital phase-locked loop (ADPLL) based on a finite impulse response (FIR) filter as the digital loop filter and implemented ...
Huirem Bharat Meitei, Manoj Kumar
doaj +1 more source
IEEE Access, 2021 An all-digital phase-locked loop (ADPLL) with a multiphase digitally controlled oscillator (DCO) incorporating the bootstrapped and interpolated schemes is proposed in this paper.
Jen-Chieh Liu, Yu-Ping Li
doaj +1 more source
Master‐Slave Topologies with Phase‐Locked Loops
Wireless Communications and Mobile Computing, Volume 2020, Issue 1, 2020., 2020 Since phase‐locked loops (PLLs) were conceived by Bellescize in 1932, their presence has become almost mandatory in any telecommunication device or network, being the essential element to recover frequency and phase information. As the technology developed, PLL appeared in several applications, such as, dense communication networks, smart grids ...
José Roberto C. Piqueira +1 more
wiley +1 more source