Results 21 to 30 of about 568 (122)

A 3.22–5.45 GHz and 199 dBc/Hz FoMT CMOS Complementary Class‐C DCO

Wireless Communications and Mobile Computing, Volume 2018, Issue 1, 2018., 2018
This paper implements a complementary Class‐C digitally controlled oscillator (DCO) with differential transistor pairs. The transistors are dynamically biased by feedback loops separately benefiting the robust oscillation start‐up with low power consumption.
Lei Ma, Na Yan, Sizheng Chen, Yangzi Liu, Hao Min, Chaojiang Li   +5 more
wiley   +1 more source

A Low Power Impedance Transparent Receiver with Linearity Enhancement Technique for IoT Applications

Wireless Communications and Mobile Computing, Volume 2018, Issue 1, 2018., 2018
A low power receiver with impedance transparent RF front end is presented. By using the 4‐path passive mixer and the active feedback of LNA, the baseband impedance profile is further transferred to receiver input. While a LO‐defined input matching is formed by RF front end, the linearity of entire receiver chain is improved.
Sizheng Chen, Tingting Shi, Lei Ma, Cheng Kang, Na Yan, Hao Min, Christian Fager   +6 more
wiley   +1 more source

Quadrature Phase-Domain ADPLL with Integrated On-line Amplitude Locked Loop Calibration for 5G Multi-band Applications [PDF]

, 2022
5th generation wireless systems (5G) have expanded frequency band coverage with the low-band 5G and mid-band 5G frequencies spanning 600 MHz to 4 GHz spectrum.
Zhang, Xiaomeng
core   +1 more source

Digital Closed‐Loop Driving Technique Using the PFD‐Based CORDIC Algorithm for a Biaxial Resonant Microaccelerometer

Journal of Sensors, Volume 2017, Issue 1, 2017., 2017
A digital closed‐loop driving technique is presented in this paper that uses the PFD‐ (phase frequency detector‐) based CORDIC (coordinate rotation digital computer) algorithm for a biaxial resonant microaccelerometer. A conventional digital closed‐loop self‐oscillation system based on the CORDIC algorithm is implemented and simulated using Simulink ...
Bo Yang, Lei Wu, Binlong Wang, Qiuhua Wang, Francesco Dell’Olio   +4 more
wiley   +1 more source

Distributed clock generator for synchronous SoC using ADPLL network [PDF]

, 2013
International audienceThis paper presents a novel architecture of on-chip clock generation employing a network of oscillators synchronized by the distributed all-digital PLLs (ADPLLs).
Akre, Jean-Michel, Anceau, François, Billoint, Olivier, Colinet, Eric, Galayko, Dimitri, Javidan, Mohammad, Juillard, Jérôme, Korniienko, Anton, Scorletti, Gérard, Shan, Chuan, Zianbetov, Eldar   +10 more
core   +4 more sources

CMOS time‐to‐digital converters for mixed‐mode signal processing

The Journal of Engineering, Volume 2014, Issue 4, Page 140-154, April 2014., 2014
This study provides an in‐depth review of the principles, architectures and design techniques of CMOS time‐to‐digital converters (TDCs). The classification of TDCs is introduced. It is followed by the examination of the parameters quantifying the performance of TDCs.
Fei Yuan
wiley   +1 more source

Design of Digital Frequency Synthesizer for 5G SDR Systems [PDF]

, 2022
The previous frequency synthesizer techniques for scalable SDR are not compatible with high end applications due to its complex computations and the intolerance over increased path interference rate which leads to an unsatisfied performance with improved
Bhaskar C., Vijaya, P. Munaswamy
core   +2 more sources

FPGA‐Based Implementation of All‐Digital QPSK Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood Frequency Estimator

International Journal of Reconfigurable Computing, Volume 2014, Issue 1, 2014., 2014
This paper presents an efficient all digital carrier recovery loop (ADCRL) for quadrature phase shift keying (QPSK). The ADCRL combines classic closed‐loop carrier recovery circuit, all digital Costas loop (ADCOL), with frequency feedward loop, maximum likelihood frequency estimator (MLFE) so as to make the best use of the advantages of the two types ...
Kaiyu Wang, Zhiming Song, Xianwei Qi, Qingxin Yan, Zhenan Tang, Nadia Nedjah   +5 more
wiley   +1 more source

A Low Power All-Digital PLL With −40dBc In-Band Fractional Spur Suppression for NB-IoT Applications

IEEE Access, 2019
This paper proposes a low-power fractional-N all-digital PLL (ADPLL) for the narrow-band Internet-of-Things applications. Multi-step lock controlling and oscillator tuning word coarse prediction algorithms help to accelerate the locking process to less ...
Na Yan, Lei Ma, Yongxin Xu, Sizheng Chen, Xusong Liu, Junhui Xiang, Hao Min   +6 more
doaj   +1 more source

A Rotary Travelling Wave Oscillator Based All-Digital PLL in 65nm CMOS [PDF]

, 2017
This thesis presents the design and implementation of an All-Digital Phase Locked Loop (ADPLL) that uses Delta-Sigma (ΔΣ) modulation, multi-phase outputs, and Dynamic Element Matching (DEM).
Cathcart, Eric
core   +2 more sources