Results 31 to 40 of about 568 (122)

480 MHz 10‐tap Clock Generator Using Edge‐Combiner DLL for USB 2.0 Applications

Journal of Electrical and Computer Engineering, Volume 2012, Issue 1, 2012., 2012
A clock generator with an edge‐combiner DLL (ECDLL) has been developed for USB 2.0 applications. The clock generator generates 480 MHz 10‐tap output signals from a 12 MHz reference signal and consists of three DLLs to shrink the design area so that it is smaller than a conventional one based on a PLL.
Takashi Kawamoto, Kazuhiro Ueda, Takayuki Noto, Woogeun Rhee   +3 more
wiley   +1 more source

A Background Jitter Calibration for ADCs Using TDC Phase Information From ADPLL

IEEE Access
The phase noise, commonly known as jitter, in Phase-Locked Loops (PLLs) is conventionally perceived as a stochastic process, necessitating a degree of tolerance in downstream circuits such as Analog-to-Digital Converters (ADCs). This paper addresses this
Haoyang Shen, Hao Zheng, Daniel O'Hare, Deepu John, Barry Cardiff   +4 more
doaj   +1 more source

Design of an All‐Digital Synchronized Frequency Multiplier Based on a Dual‐Loop (D/FLL) Architecture

VLSI Design, Volume 2012, Issue 1, 2012., 2012
This paper presents a new architecture for a synchronized frequency multiplier circuit. The proposed architecture is an all‐digital dual‐loop delay‐ and frequency‐locked loops circuit, which has several advantages, namely, it does not have the jitter accumulation issue that is normally encountered in PLL and can be adapted easily for different FPGA ...
Maher Assaad, Mohammed H. Alser, Antonio G. M. Strollo   +2 more
wiley   +1 more source

Phasemeter core for intersatellite laser heterodyne interferometry: modelling, simulations and experiments

, 2013
Inter satellite laser interferometry is a central component of future space-borne gravity instruments like LISA, eLISA, NGO and future geodesy missions.
Bykov, Iouri, Danzmann, Karsten, Delgado, Juan Jose Esteban, Gerberding, Oliver, Heinzel, Gerhard, Kullmann, Joachim, Sheard, Benjamin   +6 more
core   +1 more source

Dynamic Power Management for Neuromorphic Many-Core Systems [PDF]

, 2019
This work presents a dynamic power management architecture for neuromorphic many core systems such as SpiNNaker. A fast dynamic voltage and frequency scaling (DVFS) technique is presented which allows the processing elements (PE) to change their supply ...
Cederstroem, Love, Dixius, Andreas, Ellguth, Georg, Furber, Steve, Garside, Jim, Hartmann, Stephan, Hoeppner, Sebastian, Mayr, Christian, Neumaerker, Felix, Partzsch, Johannes, Plana, Luis, Schiefer, Stefan, Scholze, Stefan, Vogginger, Bernhard, Yan, Yexin   +14 more
core   +2 more sources

Semidigital PLL Design for Low‐Cost Low‐Power Clock Generation

Journal of Electrical and Computer Engineering, Volume 2011, Issue 1, 2011., 2011
This paper describes recent semidigital architectures of the phase‐locked loop (PLL) systems for low‐cost low‐power clock generation. With the absence of the time‐to‐digital converter (TDC), the semi‐digital PLL (SDPLL) enables low‐power linear phase detection and does not necessarily require advanced CMOS technology while maintaining a technology ...
Ni Xu, Woogeun Rhee, Zhihua Wang, Sudhakar Pamarti   +3 more
wiley   +1 more source

Noise shaping Asynchronous SAR ADC based time to digital converter [PDF]

, 2018
Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits.
Katragadda, Sowmya
core   +1 more source

RF Front‐End Circuits and Architectures for IoT/LTE‐A/5G Connectivity

, 2018
Wireless Communications and Mobile Computing, Volume 2018, Issue 1, 2018.
Yan Li, Donald Y. C. Lie, Chaojiang Li, Dixian Zhao, Christian Fager   +4 more
wiley   +1 more source

Open‐Loop Wide‐Bandwidth Phase Modulation Techniques

Journal of Electrical and Computer Engineering, Volume 2011, Issue 1, 2011., 2011
The ever‐increasing growth in the bandwidth of wireless communication channels requires the transmitter to be wide‐bandwidth and power‐efficient. Polar and outphasing transmitter topologies are two promising candidates for such applications, in future. Both these architectures require a wide‐bandwidth phase modulator.
Nitin Nidhi, Pin-En Su, Sudhakar Pamarti, Kenichi Okada   +3 more
wiley   +1 more source

Phase Locked-Loop Design of High-Order Automotive Frequency Modulated Continuous Wave Radar Based on Fast Integration Structure

IEEE Access
In recent years, frequency-modulated continuous-wave (FMCW) radars have been widely used in the automotive field to measure the relative distance and speed of external targets.
Mengwei Yang, Jinyou Chen, Changhong Shan   +2 more
doaj   +1 more source