Results 41 to 50 of about 568 (122)

Design and Implementation of FPGA based linear All Digital Phase-Locked Loop for Signal Processing Applications [PDF]

, 2012
This project presents a linear all-digital phase locked loop based on FPGA. In this ADPLL the phase detection system is realized by generating an analytic signal using a compact implementation of Hilbert transform and then simply computing the ...
Das, Abhishek, Dash, Suraj
core  

Time‐Domain ADPLL BPSK, QPSK, and 8PSK Demodulators

Journal of Electrical and Computer Engineering, Volume 2025, Issue 1, 2025.
Time‐domain all‐digital‐phase‐locked‐loop phase‐shift‐keying (PSK) demodulators are proposed for BPSK, QPSK, and 8PSK signals. The demodulator architectures are highly suitable for low‐voltage nanoscale CMOS techology. Data‐bit extraction as well as phase control for loop locking can be effectively achieved in a time domain with simple logic operators ...
Phanumas Khumsat, Thanabodee Koyphol, Tan Thongruk, Tidarat Inyod, Suman Lata Tripathi   +4 more
wiley   +1 more source

Design and Implementation of Multiple Ring Oscillator-Based TRNG Architecture by Using ADPLL

IEEE Access
A new technique for generating true random numbers by using the ADPLL (All Digital Phase Locked Loop)-based multiple ring oscillator TRNG (MURO-TRNG) is discussed in this paper.
Huirem Bharat Meitei, Manoj Kumar
doaj   +1 more source

Readout for intersatellite laser interferometry: Measuring low frequency phase fluctuations of HF signals with microradian precision

, 2015
Precision phase readout of optical beat note signals is one of the core techniques required for intersatellite laser interferometry. Future space based gravitational wave detectors like eLISA require such a readout over a wide range of MHz frequencies ...
Anders Enggaard, Carter B., Christian Diekmann, Gerhard Heinzel, Ioury Bykov, Jens Reiche, Joachim Kullmann, Juan José Esteban Delgado, Karsten Danzmann, Martin Suess, Michael Tröbs, Nils Christopher Brause, Oliver Gerberding, Oliver Jennrich, Simon Barke, Søren Møller Pedersen, Thomas S. Schwarze, Torben Rasmussen, Torben Vendt Hansen, Tröbs M., Wannamaker R. A., Zoran Sodnik   +21 more
core   +1 more source

A Low‐Power Digitally Controlled Oscillator for All Digital Phase‐Locked Loops

VLSI Design, Volume 2010, Issue 1, 2010., 2010
A low‐power and low‐jitter 12‐bit CMOS digitally controlled oscillator (DCO) design is presented. The Low‐Power CMOS DCO is designed based on the ring oscillator implemented with Schmitt trigger inverters. The proposed DCO circuit uses control codes of thermometer type to reduce jitters.
Jun Zhao, Yong-Bin Kim, Gregory D. Peterson   +2 more
wiley   +1 more source

A 3.5 to 4.7-GHz Fractional-N ADPLL With a Low-Power Time-Interleaved GRO-TDC of 6.2-ps Resolution in 65-nm CMOS Process

IEEE Access
This paper proposes a low-power design method and a low-noise phase offset calibration technique for a gated ring-oscillator time-to-digital converter (GRO-TDC), which normally consumes a large percentage of most all-digital phase-locked loop (ADPLL ...
Kyoung-Ub Cho, Joonho Gil, Chulhyun Park, Kyu-Jin Cho, Jae-Woo Shin, Eun-Seong Kim, Yun-Seong Eo, Ramesh Harjani, Nam-Young Kim, Taehyoun Oh   +9 more
doaj   +1 more source

Performance evaluation of the time delay digital tanlock loop architectures [PDF]

, 2015
This article presents the architectures, theoretical analyses and testing results of modified time delay digital tanlock loop (TDTLs) system. The modifications to the original TDTL architecture were introduced to overcome some of the limitations of the ...
Al-Kharji Al-Ali O., Al-Kharji Al-Ali O., Anani N., Best R. E., Crawford J. A., Haykin S., Mahmoud Al-Qutayri, Nader Anani, Omar Al-Kharji Al-Ali, Peeblesand P. Z., Prasad Ponnapalli, Saleh Al-Araji   +11 more
core   +1 more source

Control law synthesis for distributed multi-agent systems: Application to active clock distribution networks [PDF]

, 2011
International audienceIn this paper, the problem of active clock distribution network synchronization is considered. The network is made of identical oscillators interconnected through a distributed array of phase-locked-loops (PLLs).
Blanco, Eric, Colinet, Eric, Galayko, Dimitri, Juillard, Jerome, Korniienko, Anton, Scorletti, Gérard   +5 more
core   +4 more sources

Implementation of a secure wireless communication system using true random number generator for internet of things [PDF]

, 2023
This paper describes the design and implementation of an internet of thing (IoT)-based application that uses a true random number generator (TRNG) with an all digital phase locked loop (ADPLL) for secure wireless communication.
Kumar, Manoj, Meitei, Huirem Bharat
core   +3 more sources

Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques

IEEE Open Journal of the Solid-State Circuits Society
This article proposes an mm-wave fractional-N all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, consequently improving jitter at lower power ...
Teerachot Siriburanon, Chunxiao Liu, Jianglin Du, Robert Bogdan Staszewski   +3 more
doaj   +1 more source