Results 51 to 60 of about 568 (122)

A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL

IEEE Open Journal of the Solid-State Circuits Society
This article presents a binary frequency-shift keying (BFSK) heterodyne wake-up receiver (WuRx) with -102-dBm sensitivity at 2.4 GHz. An integrated low-power all-digital phase-locked loop (ADPLL) allows sharp filtering at the intermediate frequency (IF ...
Linsheng Zhang, Divya Duvvuri, Suprio Bhattacharya, Anjana Dissanayake, Xinjian Liu, Henry L. Bishop, Yaobin Zhang, Travis N. Blalock, Benton H. Calhoun, Steven M. Bowers   +9 more
doaj   +1 more source

Relationship between Jitter variance, Lock time and Phase noise of a second-order PLL. [PDF]

, 2019
This paper covers analytical relationships between phase noise, lock time and jitter variance. An expression is derived for Lock time in terms phase margin.
Kadambi, Govind, Mazumdar, Dipayan, Vershinin, Yuri   +2 more
core   +1 more source

Nonlinearity-Induced Spur Analysis in Fractional-N Synthesizers With ΔΣ Quantization Cancellation

IEEE Open Journal of the Solid-State Circuits Society
A fractional-N frequency synthesizer with low total jitter [e.g., <50fsrms, accounting for both phase noise (PN) and spurs] is essential for enabling the emerging 5G/6G and other high-speed wireless communication standards (e.g., WiFi-6/7).
Yizhe Hu, Weichen Tao, Robert Bogdan Staszewski   +2 more
doaj   +1 more source

Synchronized State in Networks of Digital Phase-Locked Loops [PDF]

, 2010
International audienceClock distribution networks of synchronized oscillators are an alternative approach to classical tree-like clock distribution methods.
Akre, Jean-Michel, Colinet, Eric, Galayko, Dimitri, Juillard, Jérôme   +3 more
core   +3 more sources

Linearity Calibration Method for Stochastic Time-to-Digital Converters

IEEE Access
Stochastic Time-to-Digital Converters (STDCs) can theoretically achieve very fine time resolutions utilizing random time offsets caused by device mismatch rather than relying on delay elements.
Woongdae Na, Hayun Chung
doaj   +1 more source

전원 잡음에 둔감한 고리 발진기와 디지털 위상 동기 회로 설계 [PDF]

, 2023
학위논문(석사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2023. 2. 정덕균.One of the critical blocks integrated into the PAM4-binary bridge, bridging the high-speed DRAM and the low-speed DRAM Tester, is an All-Digital Phase-Locked Loop (ADPLL).
백경민
core  

비례 이득값과 적분 이득값의 동시 최적화 기술을 사용하는 ADPLL의 설계 [PDF]

, 2023
학위논문(석사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2023. 8. 정덕균.Noise performance of a PLL is an important factor to consider when designing a PLL. The unwanted variation in the timing clock edges can deteriorate system performance.
하경준
core  

Synchronization of Coupled Boolean Phase Oscillators

, 2014
We design, characterize, and couple Boolean phase oscillators that include state-dependent feedback delay. The state-dependent delay allows us to realize an adjustable coupling strength, even though only Boolean signals are exchanged.
Gauthier, Daniel J., Rontani, Damien, Rosin, David P.   +2 more
core   +3 more sources

FPGA Implementation of ADPLL with Ripple Reduction Techniques [PDF]

, 2012
In this paper FPGA implementation of ADPLL using Verilog is presented. ADPLL with ripple reduction techniques is also simulated and implemented on FPGA.
Kusum Lata, Manoj Kumar
core   +2 more sources

Field-programmable gate array-controlled sweep velocity-locked laser pulse generator [PDF]

, 2017
This manuscript reports a FPGA-controlled sweep velocity-locked laser pulse generator (SV-LLPG) design based on an all-digital phase-locked loop (ADPLL).
Chen, Zhen, Hefferman, Gerald, Wei, Tao
core   +3 more sources