Digital command system second-order subcarrier tracking performance [PDF]
Equations to determine tracking performance for second order, phase locked loop used for subcarrier synchronization on digital command ...
Holmes, J. K., Tegnelia, C. R.
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An Effective Low Power Ring Oscillator Based All Digital Phase Locked Loop [PDF]
, 2019 The All digital phase-locked loops (ADPLL) widely employed in the data communication systems including, but not limited to, the implementation of the frequency multiplication and clock synchronization circuits.
Jeslin Jijo , J., R. Dinesh , Mr.
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고속 시리얼 링크를 위한 고리 발진기를 기반으로 하는 주파수 합성기 [PDF]
, 2022 학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022. 8. 정덕균.In this dissertation, major concerns in the clocking of modern serial links are discussed. As sub-rate, multi-standard architectures are becoming predominant, the conventional clocking methodology seems ...
김효준
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Chip Design of an All-Digital Frequency Synthesizer with Reference Spur Reduction Technique for Radar Sensing. [PDF]
Sensors (Basel), 2022 Lai WC.
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Jitter reduction techniques for digital audio. [PDF]
, 1997 by Tsang Yick Man, Steven.Thesis (M.Phil.)--Chinese University of Hong Kong, 1997.Includes bibliographical references (leaves 94-99).ABSTRACT --- p.iACKNOWLEDGMENT --- p.iiLIST OF GLOSSARY --- p.iiiChapter 1 --- INTRODUCTION --- p.1Chapter 1.1 ...
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Design and prototype of an all digital system for baseband FM multiplex signal demodulation [PDF]
, 2015 textThe continuing increase in transistor densities and operation frequencies of digital circuits is leading to the replacement of many analog circuits by their digital circuit counterparts. This trend can be attributed to the flexibility and robustness
Prabhakar, Anil, M.S. in Engineering
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Digitally Controlled Oscillator with High Timing Resolution and Low Complexity for Clock Generation. [PDF]
Sensors (Basel), 2021 Sheng D, Chen WY, Huang HT, Tai L.
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A 1.35GHz All-Digital Fractional-N PLL with Adaptive Loop Gain Controller and Fractional Divider [PDF]
, 2009 A 1.35GHz all-digital phase-locked loop (ADPLL) with an adaptively controlled loop filter and a 1/3rd-resolution fractional divider is presented. The adaptive loop gain controller (ALGC) effectively reduces the nonlinear characteristics of the bang ...
Jeong, Deog-Kyoon +4 more
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A Phased-Scaled Vernier Time-to-Digital Converter Architecture with Switchable Coarse/Fine Resolutions, Wide Range and Ultra Low Power Consumption [PDF]
, 2016 A novel phase-scaled Vernier time-to-digital converter (TDC) architecture with a switchable coarse/fine (16ps/2ps) time resolution function is presented to achieve large phase (time) detection range (32.7ns in 14 bits), fine time resolution (2ps ...
Wang, Tuoxin
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An Analog Phase Interpolation Based Fractional-N PLL [PDF]
, 2016 A novel phase-locked loop topology is presented. Compared to conventional designs, this architecture aims to increase frequency resolution and reduce quantization noise while maintaining the fractional-N benefits of high bandwidth and low phase noise up-
Bluestone, Aaron James
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