DLL Design with Wide Input Duty Cycle Range and Low Output Clock Duty Cycle Error. [PDF]
Qin B +4 more
europepmc +1 more source
Designing Neural Dynamics: From Digital Twin Modeling to Regeneration. [PDF]
Tataru CP +6 more
europepmc +1 more source
V-band ultra-fast tunable thin-film lithium niobate Fourier-domain mode-locked optoelectronic oscillator. [PDF]
Ma R +5 more
europepmc +1 more source
Research Progress of Passively Mode-Locked Fiber Lasers Based on Saturable Absorbers. [PDF]
Xie J, Liu T, Liu X, Wang F, Liu W.
europepmc +1 more source
V. Kratyuk +3 more
semanticscholar +1 more source
Optical arbitrary waveform generation (OAWG) using actively phase-stabilized spectral stitching. [PDF]
Drayss D +13 more
europepmc +1 more source
A Review on Recent Advances in Signal Processing in Interferometry. [PDF]
Wang Y, Zhao F, Luo L, Li X.
europepmc +1 more source
Modeling and Characterization of an All-Digital Phase-Locked Loop
The thesis "Modeling and Characterization of an All-Digital PLL" aims to create a behavioral model of an All-Digital Phase-Locked-Loop (ADPLL). The model should be able to perform accurate and time-effective simulations. Based on the model, a sub-block requirement will be presented as decision basis for test chip manufacturing.
Johnson, Alfred, Andersson, Fredrik
openaire +1 more source
Displacement Self-Sensing Active Magnetic Bearing Drives-An Overview. [PDF]
Yang Y, Huang Y, Peng F, Yao Y.
europepmc +1 more source
A Review on Micro-Watts All-Digital Frequency Synthesizers. [PDF]
Navaneethan V +4 more
europepmc +1 more source

