Results 11 to 20 of about 84,601 (236)
A Resolution Control Loop for TDC-Based Phase Detectors in ADPLLs
IEEE Access, 2023 This paper proposes a resolution control loop that runs in background to control the time resolution of a mid-rise Time to Digital Converter (TDC) used as a phase detector in All-Digital Phase Locked Loops (ADPLLs).
Abdelrahman Habib +2 more
doaj +1 more source
ALL-DIGITAL PHASE LOCKED LOOP (ADPLL) TOPOLOGIES FOR RFID SYSTEM APPLICATION: A REVIEW
Jurnal Teknologi, 2021 An all-digital phase locked loop (ADPLL)-based local oscillator (LO) of RF transceiver application such as radio-frequency identification (RFID) system has gained popularity by accessing the benefits in complementary metal-oxide semiconductor (CMOS ...
S. Ishak +3 more
semanticscholar +1 more source
A Fast-Locking All-Digital PLL With Triple-Stage Phase-Shifting
IEEE Access, 2021 This presents an all-digital phase-locked loop (ADPLL) system using triple-stage phase-shifting (TSPS) for fast locking. At the first stage, a phase-pulling multiplexer linearly pulls the phase of a feedback signal until the phase offset between the ...
Heon Hwa Cheong, Suhwan Kim
doaj +1 more source
Journal of Physics: Conference Series, 2021 The phase-locked loop (PLL) is a key element to capture the voltage phase of the grid in power systems with high permeability of new energy sources. An accurate phase information catcher which can be applied in the field can provide a strong support for ...
Chunyu Zhang +4 more
semanticscholar +1 more source
Sensors, 2022 5.2-GHz all-digital frequency synthesizer implemented proposed reference spur reducing with the tsmc 0.18 µm CMOS technology is proposed. It can be used for radar equipped applications and radar-communication control.
Wen-Cheng Lai
doaj +1 more source
An all-digital phase-locked loop based on variable phase accumulator
Dianzi Jishu Yingyong, 2019 This paper presents a novel all-digital phase-locked loop with variable phase accumulator circuit structure. The design of the system is completed by using EDA technology, and the system simulation experiment is carried out by using ModelSim software ...
Yang Mengwei, Tian Fan, Shan Changhong
doaj +1 more source
Design of a 3 GHz fine resolution LC DCO [PDF]
, 2017 In this thesis, the design of a fine resolution LC digitally controlled oscillator (DCO) is introduced. Two NMOS varactor banks are used to achieve 12 bits medium and fine frequency tuning.
Zhao, Xuming, active 21st century
core +1 more source
IEEE Access, 2020 This paper presents a design of 6.8 mW all digital delay locked loop (ADDLL) with digitally controlled dither cancellation (DCDC) for time to digital converter (TDC) in ranging sensors.
Muhammad Riaz Ur Rehman +6 more
doaj +1 more source
Design of all-digital phase-locked loop based on pipeline technology
Dianzi Jishu Yingyong, 2019 In order to improve the system of full digital phase-locked loop speed, reduce the power consumption of the system, and at the same time improve the dynamic performance and steady-state performance of phase-locked system,this paper proposes a full ...
Tian Fan, Yang Mengwei, Shan Changhong
doaj +1 more source
Synchronization of a renewable energy inverter with the grid [PDF]
, 2012 The design, mathematical analysis, and testing results of the architecture of a new all-digital phase-locked loop system for synchronizing a voltage source DC-AC single-phase inverter with the low voltage utility grid are presented.
Best R. E. +5 more
core +1 more source