Results 21 to 30 of about 6,822 (302)

FPGA implantations of TRNG architecture using ADPLL based on FIR filter as a loop filter

SN Applied Sciences, 2022
This article describes about the design, implementation, and analysis of a true random number generator (TRNG) employing an all-digital phase-locked loop (ADPLL) based on a finite impulse response (FIR) filter as the digital loop filter and implemented ...
Huirem Bharat Meitei, Manoj Kumar
doaj   +1 more source

A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops [PDF]

VLSI Design, 2010
A low-power and low-jitter 12-bit CMOS digitally controlled oscillator (DCO) design is presented. The Low-Power CMOS DCO is designed based on the ring oscillator implemented with Schmitt trigger inverters. The proposed DCO circuit uses control codes of thermometer type to reduce jitters.
Jun Zhao 0002, Yong-Bin Kim
openaire   +1 more source

Output-jitter performance of second-order digital bang-bang phase-locked loops with nonaccumulative reference clock jitter

, 2011
Bang-bang phase-locked loops (BBPLLs) are inherently nonlinear systems due to the binary phase detector (BPD). While they are typically used for clock and data recovery, the ongoing trend toward digital loop implementations has resulted in several ...
Tertinek, Stefan, Orla Feely, Stefan Tertinek, Feely, Orla   +3 more
core   +1 more source

FPGA-Based Implementation of All-Digital QPSK Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood Frequency Estimator

International Journal of Reconfigurable Computing, 2014
This paper presents an efficient all digital carrier recovery loop (ADCRL) for quadrature phase shift keying (QPSK). The ADCRL combines classic closed-loop carrier recovery circuit, all digital Costas loop (ADCOL), with frequency feedward loop, maximum ...
Kaiyu Wang, Zhiming Song, Xianwei Qi, Qingxin Yan, Zhenan Tang   +4 more
doaj   +1 more source

Frequency and fundamental signal measurement algorithms for distributed control and protection applications

, 2009
Increasing penetration of distributed generation within electricity networks leads to the requirement for cheap, integrated, protection and control systems.
Burt, G.M., Roscoe, Andrew J., McDonald, J.R.   +2 more
core   +1 more source

An all-digital phase-locked loop for high-speed clock generation [PDF]

IEEE Journal of Solid-State Circuits, 2003
An all-digital phase-locked loop (ADPLL) for high-speed clock generation is presented. The proposed ADPLL architecture uses both a digital control mechanism and a ring oscillator and, hence, can be implemented with standard cells. The ADPLL implemented in a 0.3-/spl mu/m one-poly-four-metal CMOS process can operate from 45 to 510 MHz and achieve worst ...
Ching-Che Chung, Chen-Yi Lee
openaire   +1 more source

Evaluation of Adaptive Loop-Bandwidth Tracking Techniques in GNSS Receivers

Sensors, 2021
Global navigation satellite system (GNSS) receivers use tracking loops to lock onto GNSS signals. Fixed loop settings limit the tracking performance against noise, receiver dynamics, and the current scenario. Adaptive tracking loops adjust these settings
Iñigo Cortés, Johannes Rossouw van der Merwe, Jari Nurmi, Alexander Rügamer, Wolfgang Felber   +4 more
doaj   +1 more source

DESIGN AND MODELLING HILBERT TRANSFORM BASED PHASE DETECTOR FOR ALL DIGITAL PHASE LOCKED LOOP

, 2016
The Phase Locked Loop (PLL) is an almost always used electronics circuit for communication systems like modulator, demodulator, frequency generator and frequency synthesizer etc. All-digital phase locked loop (ADPLL) is digital version of the PLL.
Anupama Patil*, Dr P.H.Tandel
core   +1 more source

An all-digital phase-locked loop compiler with liberty timing files [PDF]

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, 2014
In this paper, an all-digital phase-locked loop (ADPLL) compiler with liberty timing files (.lib) is presented. The proposed digitally controlled oscillator (DCO) frequency range estimation algorithm can accurately compute the frequency range of the DCO with only liberty timing files. Therefore, the proposed ADPLL compiler can generate a wide frequency
Ching-Che Chung, Duo Sheng, Chen-Han Chen   +2 more
openaire   +1 more source

3D Printing Innovations in Polymeric Porous and Patterned Architecture

Advanced Functional Materials, EarlyView.
Polymeric foams occupy a unique structural space between dense solids and open networks, where engineered void fraction governs mechanical compliance, thermal resistance, and mass transport. Additive manufacturing now enables precise spatial control over cellular architecture, unlocking designer foam structures across applications spanning crash ...
Dhanush Patil, Sri Vaishnavi Thummalapalli, Clarissa Westover, Arunachalam Ramanathan, M. Taylor Sobzcak, Roumika Patil, Qixuan Xiang, Tiantian Li, Sui Yang, Timothy E. Long, Hongyue Sun, Xianqiao Wang, Yang Liu, Kenan Song   +13 more
wiley   +1 more source