Results 11 to 20 of about 6,822 (302)
Understanding of the Coherent Demodulation with Phase-Locked Loop
The phase-locked loop (PLL) technology is a very important technology in the communication field. With the development of electronic technology toward digitalization, the phase-locked processing of signal needs to be realized in digital way.
Zhai Bingcong
doaj +2 more sources
All-Digital RF Phase-Locked Loops Exploiting Phase Prediction
This paper presents an all-digital phase-locked loop (ADPLL) architecture in a new light that allows it to significantly save power through complexity reduction of its phase locking and detection mechanisms. The natural predictive nature of the ADPLL to estimate next edge occurrence of the reference clock is exploited here to reduce the timing range ...
Jingcheng Zhuang +1 more
core +8 more sources
An all-digital phase-locked loop based on variable phase accumulator
This paper presents a novel all-digital phase-locked loop with variable phase accumulator circuit structure. The design of the system is completed by using EDA technology, and the system simulation experiment is carried out by using ModelSim software ...
Yang Mengwei, Tian Fan, Shan Changhong
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This paper presents a design of 6.8 mW all digital delay locked loop (ADDLL) with digitally controlled dither cancellation (DCDC) for time to digital converter (TDC) in ranging sensors.
Muhammad Riaz Ur Rehman +6 more
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Design of all-digital phase-locked loop based on pipeline technology
In order to improve the system of full digital phase-locked loop speed, reduce the power consumption of the system, and at the same time improve the dynamic performance and steady-state performance of phase-locked system,this paper proposes a full ...
Tian Fan, Yang Mengwei, Shan Changhong
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This paper studies a second order generalized integrator-frequency locked loop (SOGI-FLL) control scheme applicable for 3-phase alternating current/direct current (AC/DC) pulse width modulation (PWM) converters used in DC distribution systems.
Jin-Wook Kang +5 more
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This paper presents a steady-state comparison of two methods that generate an orthogonal voltage system for a single-phase Phase-Locked Loop (PLL) structure: a widely accepted one based on a Second Order Generalized Integrator (SOGI) and a new one based
Luciano Emilio Belandria +2 more
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A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems
An all-digital clock frequency multiplier that achieves excellent locking time for an energy-efficient chiplet-based system-on-chip (SoC) design is presented.
Junghoon Jin, Seungjun Kim, Jongsun Kim
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A Digitalized Silicon Microgyroscope Based on Embedded FPGA
This paper presents a novel digital miniaturization method for a prototype silicon micro-gyroscope (SMG) with the symmetrical and decoupled structure. The schematic blocks of the overall system consist of high precision analog front-end interface, high ...
Dunzhu Xia, Cheng Yu, Yuliang Wang
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For timing and synchronization system, digital phase-locked loop (DPLL) and Kalman filter all have been widely used as the clock tracking and clock correction schemes for the similar structure and properties.
Qian Gao, Chong Shen, Kun Zhang
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