Results 21 to 30 of about 84,601 (236)
An Adaptive Phase Alignment Algorithm for Cartesian Feedback Loops [PDF]
, 2010 An adaptive algorithm to correct phase misalignments in Cartesian feedback linearization loops for power amplifiers has been presented. It yields an error smaller than 0.035 rad between forward and feedback loop signals once convergence is reached ...
Gimeno Martín, Alejandro +2 more
core +2 more sources
Applied Sciences, 2018 This paper studies a second order generalized integrator-frequency locked loop (SOGI-FLL) control scheme applicable for 3-phase alternating current/direct current (AC/DC) pulse width modulation (PWM) converters used in DC distribution systems.
Jin-Wook Kang +5 more
doaj +1 more source
A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems
IEEE Access, 2022 An all-digital clock frequency multiplier that achieves excellent locking time for an energy-efficient chiplet-based system-on-chip (SoC) design is presented.
Junghoon Jin, Seungjun Kim, Jongsun Kim
doaj +1 more source
Understanding of the Coherent Demodulation with Phase-Locked Loop
MATEC Web of Conferences, 2018 The phase-locked loop (PLL) technology is a very important technology in the communication field. With the development of electronic technology toward digitalization, the phase-locked processing of signal needs to be realized in digital way.
Zhai Bingcong
doaj +1 more source
Advances in Electrical and Electronic Engineering, 2021 This paper presents a steady-state comparison of two methods that generate an orthogonal voltage system for a single-phase Phase-Locked Loop (PLL) structure: a widely accepted one based on a Second Order Generalized Integrator (SOGI) and a new one based
Luciano Emilio Belandria +2 more
doaj +1 more source
Fractional spur suppression in all-digital phase-locked loops [PDF]
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015 In this paper, fractional spur suppression techniques for all-digital PLLs (ADPLLs) are summarized. The attention is paid to the recently proposed digital-to-time converter (DTC)-based ADPLL architecture. DTC's nonlinearity dominates the fractional spurs contribution.
Peng Chen +2 more
openaire +1 more source
Hold-in, pull-in, and lock-in ranges of PLL circuits: rigorous mathematical definitions and limitations of classical theory [PDF]
, 2015 The terms hold-in, pull-in (capture), and lock-in ranges are widely used by engineers for the concepts of frequency deviation ranges within which PLL-based circuits can achieve lock under various additional conditions. Usually only non-strict definitions
Kuznetsov, N. V. +3 more
core +2 more sources
Frequency and fundamental signal measurement algorithms for distributed control and protection applications [PDF]
, 2009 Increasing penetration of distributed generation within electricity networks leads to the requirement for cheap, integrated, protection and control systems.
Burt, G.M. +2 more
core +1 more source
All-Digital RF Phase-Locked Loops Exploiting Phase Prediction
IPSJ Transactions on System LSI Design Methodology, 2014 This paper presents an all-digital phase-locked loop (ADPLL) architecture in a new light that allows it to significantly save power through complexity reduction of its phase locking and detection mechanisms. The natural predictive nature of the ADPLL to estimate next edge occurrence of the reference clock is exploited here to reduce the timing range ...
Zhuang, Jingcheng +1 more
openaire +5 more sources
Low-Jitter Clock Multiplication: a Comparioson between PLLs and DLLs [PDF]
, 2002 This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume
Beek, Remco C.H. van de +3 more
core +2 more sources