Results 31 to 40 of about 84,601 (236)
A Digitalized Silicon Microgyroscope Based on Embedded FPGA
This paper presents a novel digital miniaturization method for a prototype silicon micro-gyroscope (SMG) with the symmetrical and decoupled structure. The schematic blocks of the overall system consist of high precision analog front-end interface, high ...
Dunzhu Xia, Cheng Yu, Yuliang Wang
doaj +1 more source
FPGA implantations of TRNG architecture using ADPLL based on FIR filter as a loop filter
This article describes about the design, implementation, and analysis of a true random number generator (TRNG) employing an all-digital phase-locked loop (ADPLL) based on a finite impulse response (FIR) filter as the digital loop filter and implemented ...
Huirem Bharat Meitei, Manoj Kumar
doaj +1 more source
For timing and synchronization system, digital phase-locked loop (DPLL) and Kalman filter all have been widely used as the clock tracking and clock correction schemes for the similar structure and properties.
Qian Gao, Chong Shen, Kun Zhang
doaj +1 more source
This paper presents an efficient all digital carrier recovery loop (ADCRL) for quadrature phase shift keying (QPSK). The ADCRL combines classic closed-loop carrier recovery circuit, all digital Costas loop (ADCOL), with frequency feedward loop, maximum ...
Kaiyu Wang +4 more
doaj +1 more source
Inter satellite laser interferometry is a central component of future space-borne gravity instruments like LISA, eLISA, NGO and future geodesy missions.
Bykov, Iouri +6 more
core +1 more source
Evaluation of Adaptive Loop-Bandwidth Tracking Techniques in GNSS Receivers
Global navigation satellite system (GNSS) receivers use tracking loops to lock onto GNSS signals. Fixed loop settings limit the tracking performance against noise, receiver dynamics, and the current scenario. Adaptive tracking loops adjust these settings
Iñigo Cortés +4 more
doaj +1 more source
This paper presents a wideband fractional-N all-digital phase-locked loop (WBPLL) architecture featuring a triple-loop configuration capable of tuning frequencies from 1.9 to 6.1 GHz.
Byeongseok Kang +3 more
semanticscholar +1 more source
Demodulation Type Single-Phase PLL with DC Offset Rejection [PDF]
International audienceThis Letter proposes demodulation type PLL for phase and frequency estimation of single‐phase system that can reject DC offset. Using results from the adaptive estimation literature, this Letter proposes a linear parametric model ...
Ahmed, Hafiz, Benbouzid, Mohamed
core +1 more source
A phase-coherent technique for multiple all-digital phase-locked loops (ADPLLs) is presented and developed in this paper to target a 57–63-GHz multiple-input multiple-output (MIMO) transmitter (TX) with a digital beam-steering capability.
Mahdi Salarpour +2 more
semanticscholar +1 more source
Exploitation of Digital Filters to Advance the Single-Phase T/4 Delay PLL System [PDF]
With the development of digital signal processing technologies, control and monitoring of power electronics conversion systems have been evolving to become fully digital.
Blaabjerg, Frede +2 more
core +1 more source

