Results 141 to 150 of about 3,221,776 (178)

SMOS: A CAD‐compatible statistical model for analogue mos integrated circuit simulation

International Journal of Circuit Theory and Applications, 1992
AbstractAn analogue CAD tool capable of simulating MOS circuit performance variance caused by intra‐die variability inherent to IC fabrication processes has been developed. the nucleus of this tool is a general, CAD‐compatible, MOS statistical model called SMOS which comprehends the effects of device geometry, circuit layout and transistor bias on ...
Christopher Michael, Christopher J. Abel, Mohammed Ismail 0001   +2 more
openaire   +2 more sources

A fast reliability-aware approach for analogue integrated circuits based on Pareto fronts

2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS), 2013
Reliability becomes a critical challenge in analogue integrated circuits (ICs) design in deep sub-micron region. In order to manufacture ICs with high quality, methodology and analysis must include reliability consideration in design loop. In this paper, we propose a new statistical reliability-aware approach to evaluate circuit performance under ...
Hao Cai 0001, Hervé Petit, Jean-François Naviner   +2 more
openaire   +2 more sources

Statistical modelling of Idd testing efficiency of analogue integrated circuits

Proceedings of ISSE'95 - International Symposium on Signals, Systems and Electronics, 2002
The paper describes a new implementation of a testing-algorithm model for analogue circuits. It is based on the possibilities of HSPICE and MATLAB to manage a whole test simulation including the simulation of faulty or fault free circuits as well as their post-processing. The approach takes into account the tolerance deviations of the parameters.
openaire   +1 more source

Realistic faults mapping scheme for the fault simulation of integrated analogue CMOS circuits

Proceedings International Test Conference 1996. Test and Design Validity, 2002
A new fault modelling scheme for integrated analogue CMOS circuits referred to as Local Layout Realistic Fault Mapping is introduced. It is aimed at realistic fault assumptions prior to the final layout by investigating typical "local" layout structures of analogue designs.
openaire   +2 more sources

An intelligent design system for analogue integrated circuit

Proceedings of the European Design Automation Conference, 1990., EDAC., 2002
Georges G. E. Gielen, Koen Swings, Willy M. C. Sansen   +2 more
openaire   +2 more sources

Memristor Circuits as Linear-Gradient Systems and Discrete Analogues Preserving a First Integral

IEEE Transactions on Circuits and Systems I: Regular Papers
The paper considers a wide class of nonlinear circuits with an ideal memristor, capacitors, inductors and current or voltage sources. A fundamental dynamical property is that each memristor circuit in this class admits a first integral (invariant of motion or preserved quantity), i.e., a function which is constant along the solutions.
Mauro Di Marco, Mauro Forti, Luca Pancioni, Giacomo Innocenti, Alberto Tesi   +4 more
openaire   +3 more sources

Analogue integrated circuit technology

2003
George Clayton, Steve Winder
openaire   +1 more source

Interactive symbolic distortion analysis of analogue integrated circuits

Proceedings of the European Conference on Design Automation., 2002
Piet Wambacq, Georges G. E. Gielen, Willy Sansen   +2 more
openaire   +2 more sources

Analogue Integrated Circuits

Electronics and Power, 1986
openaire   +1 more source

The integrated circuit in analogue instruments

Microelectronics Reliability, 1968
openaire   +1 more source