Results 221 to 230 of about 4,121 (265)

Design-for-test strategies for analogue and mixed-signal integrated circuits

38th Midwest Symposium on Circuits and Systems. Proceedings, 2002
Recent advances in technology are leading to increases in the complexity and applications of analogue and mixed-signal integrated circuits. This trend has been accompanied by an increase in the complexity of associated test specifications. Furthermore, the use of functional and specification based test programs for the analogue circuitry is being ...
Olbrich, T, Liberali, V, Maloberti, F, Richardson, Andrew   +3 more
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Parametric yield enhancement of analogue integrated circuits: a new approach

1991 IEEE International Symposium on Circuits and Systems (ISCAS), 1991
Two algorithms for the parametric yield enhancement of analog ICs have been developed. Those parameters which are under the designer's control are geometric in nature and are collectively represented by a point in geometric space (G-space) whose axes are typically device widths. The aim of the yield enhancement algorithm is to move the point in G-space
M. Singha, R. Spence
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Sizing Analogue Integrated Circuits by Integer Encoding and NSGA-II

IETE Technical Review, 2017
ABSTRACTTraditional sizing approaches for analogue integrated circuits (ICs) consisting of metal-oxide-semiconductor field-effect transistors manipulate real values for the widths (W) and lengths (L), thus requiring a post-processing step to round them to multiples of lambda, i.e. the IC fabrication technology.
A. C. Sanabria-Borbón, E. Tlelo-Cuautle
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SMOS: A CAD‐compatible statistical model for analogue mos integrated circuit simulation

International Journal of Circuit Theory and Applications, 1992
AbstractAn analogue CAD tool capable of simulating MOS circuit performance variance caused by intra‐die variability inherent to IC fabrication processes has been developed. the nucleus of this tool is a general, CAD‐compatible, MOS statistical model called SMOS which comprehends the effects of device geometry, circuit layout and transistor bias on ...
Christopher Michael, Christopher J. Abel, Mohammed Ismail 0001   +2 more
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A fast reliability-aware approach for analogue integrated circuits based on Pareto fronts

2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS), 2013
Reliability becomes a critical challenge in analogue integrated circuits (ICs) design in deep sub-micron region. In order to manufacture ICs with high quality, methodology and analysis must include reliability consideration in design loop. In this paper, we propose a new statistical reliability-aware approach to evaluate circuit performance under ...
Hao Cai 0001, Hervé Petit, Jean-François Naviner   +2 more
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Statistical modelling of Idd testing efficiency of analogue integrated circuits

Proceedings of ISSE'95 - International Symposium on Signals, Systems and Electronics, 2002
The paper describes a new implementation of a testing-algorithm model for analogue circuits. It is based on the possibilities of HSPICE and MATLAB to manage a whole test simulation including the simulation of faulty or fault free circuits as well as their post-processing. The approach takes into account the tolerance deviations of the parameters.
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System level performance and yield optimisation for analogue integrated circuits. [PDF]

, 2009
Advances in silicon technology over the last decade have led to increased integration of analogue and digital functional blocks onto the same single chip. In such a mixed signal environment, the analogue circuits must use the same process technology as their digital neighbours.
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Realistic faults mapping scheme for the fault simulation of integrated analogue CMOS circuits

Proceedings International Test Conference 1996. Test and Design Validity, 2002
A new fault modelling scheme for integrated analogue CMOS circuits referred to as Local Layout Realistic Fault Mapping is introduced. It is aimed at realistic fault assumptions prior to the final layout by investigating typical "local" layout structures of analogue designs.
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An intelligent design system for analogue integrated circuit

Proceedings of the European Design Automation Conference, 1990., EDAC., 2002
Georges G. E. Gielen, Koen Swings, Willy M. C. Sansen   +2 more
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An approach to design-for-testability automation of analogue integrated circuits using OBIST strategy

2016 5th Mediterranean Conference on Embedded Computing (MECO), 2016
© 2016 IEEE.This paper is mainly focused on the task of design-for-testability (DFT) automation with emphasis on OBIST strategy for analog integrated circuits. The design procedures according to DFT flow are proposed. Three possible structural solutions for reconfiguration of original circuit into oscillator are considered.
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