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High Temperature Digital and Analogue Integrated Circuits in Silicon Carbide
Materials Science Forum, 2013Silicon Carbide devices are capable of operating as a semiconductor at high temperatures and this capability is being exploited today in discrete power components, bringing system advantages such as reduced cooling requirements [1]. Therefore there is an emerging need for control ICs mounted on the same modules and being capable of operating at the ...
R.A.R. Young +7 more
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Electrothermal Simulation of Analogue Integrated Circuits With Ets
1997Nowadays, high-power devices are integrated together with complex digital and high performance analogue circuits on the same chip. Inappropriate design and/or layout cause major problems with maximum temperature and temperature gradients between components.
W. van Petegem, B. Geeraerts, W. Sansen
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Sizing Analogue Integrated Circuits by Integer Encoding and NSGA-II
IETE Technical Review, 2017ABSTRACTTraditional sizing approaches for analogue integrated circuits (ICs) consisting of metal-oxide-semiconductor field-effect transistors manipulate real values for the widths (W) and lengths (L), thus requiring a post-processing step to round them to multiples of lambda, i.e. the IC fabrication technology.
A. C. Sanabria-Borbón, E. Tlelo-Cuautle
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Future of Analogue Integrated Circuit Design
1993Analogue integrated circuit design has played an important role in the development of integrated circuit technology. As the level of integration increased in integrated circuit technology, digital circuit implementation became more desirable than analogue circuit implementation because of its robustness and simplicity of design. However, an all-digital
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A design for testability approach for nano-CMOS analogue integrated circuits
International Journal of Electronics, 2013Dependability requirements must be considered from the beginning when designing safety-critical systems. Therefore, testing should even be considered earlier, intertwined with the design process. The process of designing for better testability is called design for testability (DfT).
Mouna Karmani +4 more
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Parametric yield enhancement of analogue integrated circuits: a new approach
1991 IEEE International Symposium on Circuits and Systems (ISCAS), 1991Two algorithms for the parametric yield enhancement of analog ICs have been developed. Those parameters which are under the designer's control are geometric in nature and are collectively represented by a point in geometric space (G-space) whose axes are typically device widths. The aim of the yield enhancement algorithm is to move the point in G-space
M. Singha, R. Spence
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Design-for-test strategies for analogue and mixed-signal integrated circuits
38th Midwest Symposium on Circuits and Systems. Proceedings, 2002Recent advances in technology are leading to increases in the complexity and applications of analogue and mixed-signal integrated circuits. This trend has been accompanied by an increase in the complexity of associated test specifications. Furthermore, the use of functional and specification based test programs for the analogue circuitry is being ...
Olbrich, T +3 more
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Experimental validation of electrothermal simulations using SETIPIC for analogue integrated circuits
Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics, 2002This paper presents the validation of SETIPIC-an electrothermal simulator for power integrated circuits. SETIPIC works by alternation of electrical simulations, using a SPICE-like simulator and thermal simulations using PICMOST-a three-dimensional thermal simulator we wrote to obtain the thermal distribution on the layout surface in a transient or ...
J. Ecrabey +6 more
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Precision, low power, analogue TCXO using a single integrated circuit
10th International Conference on European Frequency and Time, 1996We have designed a single chip TCXO which is capable of temperature compensation to better than /spl plusmn/0.1 ppm over -50 to +90/spl deg/C. Off-chip components are limited to a decoupling capacitor, the crystal, and a filter capacitor for low-noise applications.
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Statistical modelling of Idd testing efficiency of analogue integrated circuits
Proceedings of ISSE'95 - International Symposium on Signals, Systems and Electronics, 2002The paper describes a new implementation of a testing-algorithm model for analogue circuits. It is based on the possibilities of HSPICE and MATLAB to manage a whole test simulation including the simulation of faulty or fault free circuits as well as their post-processing. The approach takes into account the tolerance deviations of the parameters.
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