Results 11 to 20 of about 562 (143)

Degradation Measurement and Modelling under Ageing in a 16 nm FinFET FPGA [PDF]

open access: yesMicromachines, 2023
Most of the latest generation of integrated circuits use FinFET transistors for their performance, but what about their reliability? Does the architectural evolution from planar MOSFET to FinFET transistor have any effect on the integrated circuit ...
Justin Sobas, François Marc
doaj   +2 more sources

Comprehensive analysis of In0.53Ga0.47As SOI-FinFET for enhanced RF/wireless performance [PDF]

open access: yesFrontiers in Electronics
This paper comprehensively analyses the RF (Radio Frequency) and wireless performance characteristics of high-k In0.53Ga0.47As silicon-on-insulator FinFET (InGaAs-SOI-FinFET).
Priyanka Agrwal, Ajay Kumar
doaj   +3 more sources

Comprehensive Investigation of Truncated Fin GaN FinFET for Improved Analog/RF Performance

open access: yesIEEE Open Journal of Nanotechnology
This work presents an analysis of the performance of Gallium Nitride Truncated Fin FinFETs (GaN-TF-FinFET) and compares them with conventional (C) FinFET, TF-FinFET, and silicon-on-insulator (SOI) TF-FinFET in analog and RF applications by using advanced
Praween Kumar Srivastava   +2 more
doaj   +2 more sources

A Stepped-Spacer FinFET Design for Enhanced Device Performance in FPGA Applications. [PDF]

open access: yesMicromachines (Basel)
As transistor dimensions continue to scale below 10 nm, traditional MOSFET architectures face increasing limitations from short-channel effects, gate leakage, and variability.
Zareiee M, Mehrad M, Tawfik A.
europepmc   +3 more sources

High-Quality Recrystallization of Amorphous Silicon on Si (100) Induced via Laser Annealing at the Nanoscale

open access: yesNanomaterials, 2023
At sub-3 nm nodes, the scaling of lateral devices represented by a fin field-effect transistor (FinFET) and gate-all-around field effect transistors (GAAFET) faces increasing technical challenges.
Zhuo Chen   +14 more
doaj   +1 more source

Self-Consistent Enhanced S/D Tunneling Implementation in a 2D MS-EMC Nanodevice Simulator [PDF]

open access: yes, 2021
The implementation of a source to drain tunneling in ultrascaled devices using MS-EMC has traditionally led to overestimated current levels in the subthreshold regime.
Asenov, Asen   +6 more
core   +3 more sources

Comparison of Temperature Dependent Carrier Transport in FinFET and Gate-All-Around Nanowire FET

open access: yesApplied Sciences, 2020
The temperature dependent carrier transport characteristics of n-type gate-all-around nanowire field effect transistors (GAA NW-FET) on bulk silicon are experimentally compared to bulk fin field effect transistors (FinFET) over a wide range of ...
Soohyun Kim   +9 more
doaj   +1 more source

Ultra-Low-Power FinFETs-Based TPCA-PUF Circuit for Secure IoT Devices

open access: yesSensors, 2021
Low-power and secure crypto-devices are in crucial demand for the current emerging technology of the Internet of Things (IoT). In nanometer CMOS technology, the static and dynamic power consumptions are in a very critical challenge.
Cancio Monteiro, Yasuhiro Takahashi
doaj   +1 more source

Nano transistores de efecto de campo tipo aleta para aplicaciones digitales [PDF]

open access: yes, 2021
The aim of this work is providing to students of electronics, computing and related areas, an overview of the construction and behavior of fin field effect transistors (FinFETs), which are tiny devices, with gate length in the nanometer range, they are ...
García-Rivera, Max   +5 more
core   +2 more sources

Ultra-Low Power Oscillator Collapse Physical Unclonable Function Based on FinFET

open access: yesIEEE Access, 2021
The main purpose of this paper is to achieve ultra-low power Physical Unclonable Function (PUF) to meet the requirements for Internet of Things (IoT) applications.
Amin A. Zayed   +3 more
doaj   +1 more source

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