Results 21 to 30 of about 544 (110)

The Evolution of Semiconductor Devices: From Transistors to Quantum and Neuromorphic Computing

open access: yesphysica status solidi (RRL) – Rapid Research Letters, Volume 20, Issue 8, August 2026.
This review presents the evolution of semiconductor devices from BJTs to fin field‐effect transistors (FinFETs), nanowire, and carbon nanotube transistors. It highlights emerging materials, including SiC and GaN, and examines neuromorphic and quantum computing, industry applications, performance benchmarks, challenges, and future directions.
Manoharan Subramanian   +6 more
wiley   +1 more source

Physical Modeling and Design of a Nonvolatile Optically Gated High‐Power Diamond Transistor

open access: yesphysica status solidi (a), Volume 223, Issue 11, 10 June 2026.
We introduce a diamond optically gated field effect transistor (DOGFET) which combines high‐speed high‐power operation with exotic single transistor memory. The transistor uses deep level donor type nitrogen traps in type 1b diamond that are optically excited to enable electrostatic gating of the device.
Soumak Nandi   +9 more
wiley   +1 more source

Low‐temperature SOI SiGe/Si superlattice FinFET with omega‐shaped channel and self‐allied silicide for 3D sequential IC

open access: yesElectronics Letters
In this letter, to improve the performance and reduce leakage currents of bulk low‐temperature multi‐layer SiGe/Si superlattice (SL) fin field‐effect transistors (FinFETs), a p‐type omega‐shaped channel (Ω‐channel) SL FinFET is realized by etching a Si ...
Xu‐Lei Qin   +10 more
doaj   +1 more source

Understanding Frequency Dependence of Trap Generation Under AC Positive Bias Temperature Instability Stress in Si n-FinFETs

open access: yesIEEE Journal of the Electron Devices Society
In this paper, the frequency (f) dependence of trap generation in Si n-channel fin field-effect transistors (n-FinFETs) under AC positive bias temperature instability (PBTI) stress is investigated by fast direct-current current-voltage (DCIV) method and ...
Yunfei Shi   +14 more
doaj   +1 more source

Plasma‐Sequence‐Engineered Atomic Layer Deposition of Ultra‐Thin SiNx for Enhanced Etching Resistance in Extreme Ultraviolet Pellicles

open access: yesAdvanced Materials Interfaces, Volume 13, Issue 11, 9 June 2026.
Plasma‐sequence‐engineered ALD (PSE‐ALD), based on sequential NH3 and N2 plasma pulses, enables ultrathin, dense SiNx films. ToF‐MS analysis confirms ligand removal via HCl evolution, while increased film density indicates network densification. The resulting SiNx coating provides robust protection of graphite under H2 plasma exposure.
Hye‐Young Kim   +7 more
wiley   +1 more source

Atomic Layer Deposition in Transistors and Monolithic 3D Integration

open access: yesAdvanced Functional Materials, Volume 36, Issue 41, 21 May 2026.
Transistors are fundamental building blocks of modern electronics. This review summarizes recent progress in atomic layer deposition (ALD) for the synthesis of two‐dimensional (2D) metal oxides and transition‐metal dichalcogenides (TMDCs), with particular emphasis on their enabling role in monolithic three‐dimensional (M3D) integration for next ...
Yue Liu   +5 more
wiley   +1 more source

Molecular Design Toward High‐Performance Solution‐Processable Push–Pull Zinc(II) Porphyrin‐Based Resistive Memory Devices: From Binary to Ternary Memory Behavior

open access: yesSmall Science, Volume 6, Issue 5, May 2026.
A series of zinc(II) porphyrin‐based D−A complexes is employed to fabricate solution‐processable resistive memory devices. The utilization of an electron‐donating π‐bridge or a weak electron‐donating moiety is able to turn on an extra resistive state to realize ternary memory performance, demonstrating the relationship between memory behavior and ...
Ka Wai Kwong   +5 more
wiley   +1 more source

Impacts of Local Oxide Trapped Charge on Electrical and Capacitance Characteristics of SOI FinFet

open access: yesEast European Journal of Physics
In this work, the influence of the local oxide trapped charge on the transfer Id-Vg characteristics and capacitance of the gatetoI. INTRODUCTION source (drain) connection of the silicon-on-insulator (SOI) structure-based FinFET is simulated.
Atabek Atamuratov   +5 more
doaj   +1 more source

Dielectric and Gate Metal Engineering for Threshold Voltage Modulation in Enhancement Mode Monolayer MoS2 Field Effect Transistors

open access: yesAdvanced Materials, Volume 38, Issue 21, 13 April 2026.
Enhancement‐mode monolayer MoS2 FETs with low threshold voltage are essential for low‐power electronics. The threshold voltage can be tuned by the gate metal work function when the semiconductor/dielectric interface is clean. Interfaces between monolayer MoS2 and ZrO2 or hBN allow effective work‐function modulation of the threshold voltage, in contrast
Lixin Liu   +10 more
wiley   +1 more source

Utilizing MRAMs With Low Resistance and Limited Dynamic Range for Efficient MAC Accelerator

open access: yesIEEE Open Journal of Nanotechnology
The recent advancements in data mining, machine learning algorithms and cognitive systems have necessitated the development of neuromorphic processing engines which may enable resource and computationally intensive applications on the internet-of-Things (
Sateesh   +2 more
doaj   +1 more source

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