Results 21 to 30 of about 19,628,440 (150)

Comparison of bulk FinFET and SOI FinFET

, 2018
In this study, we compare the differences and advantages between Bulk FinFET and SOI FinFET. The results are simulated by using the ISE TCAD software.
Lin Yu-Hsien, Yu-Hsien Lin, Chen Ying-Yu, Ying-Yu Chen   +3 more
core   +1 more source

A Compendium of Logic Gates Based on Reconfigurable Three‐Independent‐Gate Transistors Realized in FDSOI Hardware

Advanced Electronic Materials, EarlyView.
This work electrically characterizes sixteen logic gates built from three‐independent‐gate reconfigurable transistors fabricated on full‐scale 300 mm wafers using the industrial 22 nm fully depleted FDSOI process of GlobalFoundries. Static and time‐resolved measurements confirm correct operation, including a 1‐bit adder and reconfigurable AOI/OAI ...
Juan P. Martinez, Yuxuan He, Giulio Galderisi, Violetta Sessi, Niladri Bhattacharjee, Peter Baars, Kerstin Poenisch, Annekathrin Zeun, Konstantin Li, Fernando Koch, Binit Syamal, Thomas Mikolajick, Jens Trommer   +12 more
wiley   +1 more source

AI‐Guided Co‐Optimization of Advanced Field‐Effect Transistors: Bridging Material, Device, and Fabrication Design

Advanced Intelligent Discovery, EarlyView.
This article outlines how artificial intelligence could reshape the design of next‐generation transistors as traditional scaling reaches its limits. It discusses emerging roles of machine learning across materials selection, device modeling, and fabrication processes, and highlights hierarchical reinforcement learning as a promising framework for ...
Shoubhanik Nath, Shauryaraj K. Jilkar, Aditya Udgaonkar, Yu (Joe) Lu, Ali Mesbah   +4 more
wiley   +1 more source

Parametric Analysis of Spiking Neurons in 16 nm Fin Field‐Effect Transistor Technology

Advanced Intelligent Discovery, EarlyView.
Energy efficient computing has driven a shift toward brain‐inspired neuromorphic hardware. This study explores the design of three distinct silicon neuron topologies implemented in 16 nm fin field‐Effect transistor technology. While the Axon‐Hillock design achieves gigahertz throughput, its functional fragility persists. The Morris–Lecar model captures
Logan Larsh, Raiyan Siddique, Sarah S. Sharif, Yaser Mike Banad   +3 more
wiley   +1 more source

Temperature sensitivity based on channel length of FinFET transistor [PDF]

, 2018
This paper presents the temperature sensitivity of the gate length-based fin field effect transistor (FinFET) and the possibility of using such a transistor as a nano-temperature sensor.
Hashim, Yasir, Yousif Atalla, Abdul Nasir, Abd Ghafar, A.N.A. Ghafar, Atalla, Yousif, Yasir Hashim   +5 more
core   +2 more sources

Design and investigation of a delay controlled ALU employing FinFET& CNTFET technologies

e-Prime: Advances in Electrical Engineering, Electronics and Energy
The Arithmetic and Logic Unit (ALU) is a crucial logical element of real-time semiconductor devices. Conventional ALUs that are built using Complementary Metal Oxide Semiconductor (CMOS) technology exhibit increased power usage and processing delays ...
Ch JayaPrakash, Ashok Battula, SurendraBabu Velagaleti   +2 more
doaj   +1 more source

Bayesian Optimization–Reinforcement Learning Hybrid Framework for a‐IGZO Thin‐Film Transistor Compact Model Parameter Extraction in 2T0C Dynamic Random Access Memory Applications

Advanced Intelligent Systems, EarlyView.
A training‐free two‐stage BO–RL framework extracts compact model parameters for a‐IGZO TFTs, reaching BO‐level fitting quality at a constant per‐simulation optimization cost. Bayesian optimization performs exploration and provides an optimized starting point.
Seunghyun Son, Taejun Ha, Taeyoung Nam, Yoonyoung Chung, Sunmean Kim   +4 more
wiley   +1 more source

Revisiting Dopant Deactivation In Silicon Nanostructures

Advanced Physics Research, EarlyView.
Dopant activation is essential for the operation of semiconductor devices. On the nanoscale, however, quantum confinement and dielectric mismatch impede dopant activation. Here, we study the ionization of phosphorous in ultrathin silicon films embedded in different dielectric environments.
J. Knoch, D. König, M. Frentzen, Y.‐C. Chang, D. Hiller   +4 more
wiley   +1 more source

Two‐Dimensional Heterostructures: From Controlled Synthesis to Post‐Moore Device Applications

Information &Functional Materials, EarlyView.
This schematic summarizes four typical configurations of two‐dimensional (2D) heterostructures. It also demonstrates their core applications in high‐performance logic transistors, neuromorphic computing, ultra‐broadband photodetection, and multifunctional integrated devices, visually illustrating the diverse development prospects of 2D heterostructures
Jianing Xie, Zijian Niu, Baihui Zhang, Zhengwei Zhang   +3 more
wiley   +1 more source

Si- and Ge-FinFET Inverter Circuits Optimization Based on Driver to Load Transistor Fin Ratio [PDF]

, 2021
This paper proposes a novel method to adaptively select the best driver to load transistor fin ratio of six transistor (6T) FinFET-SRAMs according to the best values of noise margins and inflection voltages with a comparison between using Si and Ge ...
Hashim, Yasir, Mawlood, Safwan, Safwan Mawlood Hussein, null null, Yasir Hashim   +4 more
core   +1 more source