Results 11 to 20 of about 544 (110)

Carrier Mapping in Sub-2nm Node Nanosheet Transistors with Scanning Spreading Resistance Microscopy. [PDF]

Small Methods
Within this work, advancements in scanning spreading resistance microscopy (SSRM) allow charge carrier mapping within 5.5 nm‐thick nanosheet channels. Devices subjected to rapid thermal annealing at 950°C show ∼ 5 nm enhanced phosphorus diffusion, with profiles in close agreement with semi‐atomistic process simulations.
Pondini A, Eyben P, Wouters L, Minj A, Hantschel T, Matagne P, Mitard J, Verhulst A.   +7 more
europepmc   +2 more sources

Comprehensive Investigation of Truncated Fin GaN FinFET for Improved Analog/RF Performance

IEEE Open Journal of Nanotechnology
This work presents an analysis of the performance of Gallium Nitride Truncated Fin FinFETs (GaN-TF-FinFET) and compares them with conventional (C) FinFET, TF-FinFET, and silicon-on-insulator (SOI) TF-FinFET in analog and RF applications by using advanced
Praween Kumar Srivastava, Atul Kumar, Ajay Kumar   +2 more
doaj   +1 more source

Performance assessment of InGaAs–SOI–FinFET for enhancing switching capability using high-k dielectric

Memories - Materials, Devices, Circuits and Systems
In this work, a high-k In0.53Ga0.47As silicon-on-insulator FinFET (InGaAs–SOI–FinFET) is presented for high-switching and ultra-low power applications at 7 nm gate length.
Priyanka Agrwal, Ajay Kumar
doaj   +1 more source

Comprehensive analysis of In0.53Ga0.47As SOI-FinFET for enhanced RF/wireless performance

Frontiers in Electronics
This paper comprehensively analyses the RF (Radio Frequency) and wireless performance characteristics of high-k In0.53Ga0.47As silicon-on-insulator FinFET (InGaAs-SOI-FinFET).
Priyanka Agrwal, Ajay Kumar
doaj   +1 more source

High-k dielectrics on (100) and (110) n-InAs: Physical and electrical characterizations

AIP Advances, 2014
Two high-k dielectric materials (Al2O3 and HfO2) were deposited on n-type (100) and (110) InAs surface orientations to investigate physical properties of the oxide/semiconductor interfaces and the interface trap density (Dit).
C. H. Wang, G. Doornbos, G. Astromskas, G. Vellianitis, R. Oxland, M. C. Holland, M. L. Huang, C. H. Lin, C. H. Hsieh, Y. S. Chang, T. L. Lee, Y. Y. Chen, P. Ramvall, E. Lind, W. C. Hsu, L.-E. Wernersson, R. Droopad, M. Passlack, C. H. Diaz   +18 more
doaj   +1 more source

A Compendium of Logic Gates Based on Reconfigurable Three‐Independent‐Gate Transistors Realized in FDSOI Hardware

Advanced Electronic Materials, EarlyView.
This work electrically characterizes sixteen logic gates built from three‐independent‐gate reconfigurable transistors fabricated on full‐scale 300 mm wafers using the industrial 22 nm fully depleted FDSOI process of GlobalFoundries. Static and time‐resolved measurements confirm correct operation, including a 1‐bit adder and reconfigurable AOI/OAI ...
Juan P. Martinez, Yuxuan He, Giulio Galderisi, Violetta Sessi, Niladri Bhattacharjee, Peter Baars, Kerstin Poenisch, Annekathrin Zeun, Konstantin Li, Fernando Koch, Binit Syamal, Thomas Mikolajick, Jens Trommer   +12 more
wiley   +1 more source

AI‐Guided Co‐Optimization of Advanced Field‐Effect Transistors: Bridging Material, Device, and Fabrication Design

Advanced Intelligent Discovery, EarlyView.
This article outlines how artificial intelligence could reshape the design of next‐generation transistors as traditional scaling reaches its limits. It discusses emerging roles of machine learning across materials selection, device modeling, and fabrication processes, and highlights hierarchical reinforcement learning as a promising framework for ...
Shoubhanik Nath, Shauryaraj K. Jilkar, Aditya Udgaonkar, Yu (Joe) Lu, Ali Mesbah   +4 more
wiley   +1 more source

Parametric Analysis of Spiking Neurons in 16 nm Fin Field‐Effect Transistor Technology

Advanced Intelligent Discovery, EarlyView.
Energy efficient computing has driven a shift toward brain‐inspired neuromorphic hardware. This study explores the design of three distinct silicon neuron topologies implemented in 16 nm fin field‐Effect transistor technology. While the Axon‐Hillock design achieves gigahertz throughput, its functional fragility persists. The Morris–Lecar model captures
Logan Larsh, Raiyan Siddique, Sarah S. Sharif, Yaser Mike Banad   +3 more
wiley   +1 more source

Design and investigation of a delay controlled ALU employing FinFET& CNTFET technologies

e-Prime: Advances in Electrical Engineering, Electronics and Energy
The Arithmetic and Logic Unit (ALU) is a crucial logical element of real-time semiconductor devices. Conventional ALUs that are built using Complementary Metal Oxide Semiconductor (CMOS) technology exhibit increased power usage and processing delays ...
Ch JayaPrakash, Ashok Battula, SurendraBabu Velagaleti   +2 more
doaj   +1 more source

An Innovative Approach to Multi‐Valued Logic

IEEJ Transactions on Electrical and Electronic Engineering, EarlyView.
The current generation of computer systems operates on the principles of binary logic, which encompasses both logical and arithmetic operations. However, silicon technology has reached its peak performance, prompting researchers to explore alternative methods for enhancing computational efficiency. One such method is the adoption of Multi‐Valued Logic (
Ali Mokhtari, Peyman Kabiri
wiley   +1 more source