Results 31 to 40 of about 19,628,440 (150)

Low‐temperature SOI SiGe/Si superlattice FinFET with omega‐shaped channel and self‐allied silicide for 3D sequential IC

Electronics Letters
In this letter, to improve the performance and reduce leakage currents of bulk low‐temperature multi‐layer SiGe/Si superlattice (SL) fin field‐effect transistors (FinFETs), a p‐type omega‐shaped channel (Ω‐channel) SL FinFET is realized by etching a Si ...
Xu‐Lei Qin, Guan‐Qiao Sang, Lei Cao, Qing‐Kun Li, Ren‐Jie Jiang, Yan‐Zhao Wei, Jun‐Feng Li, Jia‐Xin Yao, Mei‐He Zhang, Qing‐Zhu Zhang, Hua‐Xiang Yin   +10 more
doaj   +1 more source

Understanding Frequency Dependence of Trap Generation Under AC Positive Bias Temperature Instability Stress in Si n-FinFETs

IEEE Journal of the Electron Devices Society
In this paper, the frequency (f) dependence of trap generation in Si n-channel fin field-effect transistors (n-FinFETs) under AC positive bias temperature instability (PBTI) stress is investigated by fast direct-current current-voltage (DCIV) method and ...
Yunfei Shi, Hao Chang, Hong Yang, Qiangzhu Zhang, Qianqian Liu, Bo Tang, Longda Zhou, Zhigang Ji, Junjie Li, Xiaobin He, Junfeng Li, Huaxiang Yin, Xiaolei Wang, Jun Luo, Wenwu Wang   +14 more
doaj   +1 more source

Low‐Frequency Noise and Stability in Electrolyte‐Gated Nanoscale Silicon Field‐Effect Transistor Sensors

Small Methods, EarlyView.
Electrolyte‐gated nanoscale silicon field‐effect transistor sensors provide exceptional charge sensitivity and direct electrical readout. However, their sensing accuracy is fundamentally limited by low‐frequency noise and baseline drift. This review examines the origins of noise and drift in these sensors, summarizes the key mitigation strategies, and ...
Yingtao Yu, Zheqiang Xu, Yihan Wang, Qitao Hu, Paul Solomon, Zhen Zhang   +5 more
wiley   +1 more source

Impact of channel line-edge roughness on junctionless FinFET

, 2015
The impact of channel line-edge roughness (LER) on Junctionless FinFET device (JL-FinFET) is investigated by using the 3-D statistical simulation. Then the substantial influence of its narrowest width of the JL-FinFET is defined and presented.
Zhang, Lining, Lining Zhang, Xiao, Ying, Ying Xiao, Zhang, Baili, Cui, Xiaole, Baili Zhang, Xinnan Lin, Lou, Haijun, Lin, Xinnan, Haijun Lou, Xiaole Cui   +11 more
core   +1 more source

An Innovative Approach to Multi‐Valued Logic

IEEJ Transactions on Electrical and Electronic Engineering, EarlyView.
The current generation of computer systems operates on the principles of binary logic, which encompasses both logical and arithmetic operations. However, silicon technology has reached its peak performance, prompting researchers to explore alternative methods for enhancing computational efficiency. One such method is the adoption of Multi‐Valued Logic (
Ali Mokhtari, Peyman Kabiri
wiley   +1 more source

Two‐Dimensional Flash Memory: Materials, Interfaces, and Storage–Computing Convergence

Advanced Science, Volume 13, Issue 59, 23 October 2026.
We systematically summarize recent advances in 2D flash memory, highlighting how interface and material engineering can overcome the conventional trade‐offs among speed, power consumption, and reliability in silicon‐based flash, and outlining its potential for high‐performance memory and in‐memory computing applications.
Zhiyuan Wang, Fanyi Meng, Fanying Meng, Shida Huo, Junxi Xu, Yaohui Wang, Yuexuan Ma, Yuan Xie, Xiaodong Hu, Caofeng Pan, Enxiu Wu   +10 more
wiley   +1 more source

FinFET SRAM hardening through design and technology parameters considering process variations [PDF]

, 2013
Radiation-induced soft errors have become one of the most important reliability concerns in the nanometer regime. In this paper, we analyze two alternatives to improve FinFET-based SRAM cell hardening.
Víctor Hugo Champac Vilela, Héctor Luis Villacorta Minaya   +1 more
core  

Impacts of Local Oxide Trapped Charge on Electrical and Capacitance Characteristics of SOI FinFet

East European Journal of Physics
In this work, the influence of the local oxide trapped charge on the transfer Id-Vg characteristics and capacitance of the gatetoI. INTRODUCTION source (drain) connection of the silicon-on-insulator (SOI) structure-based FinFET is simulated.
Atabek Atamuratov, Ibroximjon Karimov, Mirzabahrom Foziljonov, Azamat Abdikarimov, Odilbek Atamuratov, Makhkam Khalilloev   +5 more
doaj   +1 more source

Reconfigurable Ternary Logic‐In‐Memory With Organic Antiambipolar Transistor

Advanced Electronic Materials, Volume 12, Issue 19, 12 October 2026.
We develop a ternary logic‐in‐memory with an organic antiambipolar transistor combining a ternary inverter and ternary nonvolatile memory in the same circuit. The memory function of the circuit enables electrical reconfiguration to obtain standard, negative, and positive ternary inverters in the same device.
Ryoma Hayakawa, Taiga Kijima, Yuho Yamamoto, Yoichi Yamada, Yutaka Wakayama   +4 more
wiley   +1 more source

Характеристики комбінованого (Si та Ge) інвертора FinFET-CMOS на основі співвідношення транзисторів навантаження до драйверу [PDF]

, 2022
У статті пропонується новий метод адаптивного вибору найкращого співвідношення плавців драйвера до навантажувального транзистора логічного інвертора CMOS FinFET відповідно до кращих значень запасу по шуму та напруги перегину з порівнянням при ...
Safwan, Mawlood Hussein, Yasir, Hashim, Hashim, Yasir, Mawlood, Safwan   +3 more
core   +1 more source