Results 81 to 90 of about 544 (110)

Highly Selective Isotropic Etching of Si to SiGe Using CF₄/O₂/N₂ Plasma for Advanced GAA Nanosheet Transistor. [PDF]

Nanomaterials (Basel)
Li J, Sun X, Huang Z, Zhang DW.
europepmc   +1 more source

A Physics-Consistent Framework for Semiconductor Device Reliability Including Multiple Degradation Mechanisms. [PDF]

Micromachines (Basel)
Bernstein JB, Avraham T, Wang B.
europepmc   +1 more source

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology. [PDF]

Nanomaterials (Basel)
Radamson HH, Miao Y, Zhou Z, Wu Z, Kong Z, Gao J, Yang H, Ren Y, Zhang Y, Shi J, Xiang J, Cui H, Lu B, Li J, Liu J, Lin H, Xu H, Li M, Cao J, He C, Duan X, Zhao X, Su J, Du Y, Yu J, Wu Y, Jiang M, Liang D, Li B, Dong Y, Wang G.   +30 more
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New structure transistors for advanced technology node CMOS ICs. [PDF]

Natl Sci Rev
Zhang Q, Zhang Y, Luo Y, Yin H.
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Two-Dimensional Materials, the Ultimate Solution for Future Electronics and Very-Large-Scale Integrated Circuits. [PDF]

Nanomicro Lett
Qin L, Wang L.
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High-density via RRAM cell with multi-level setting by current compliance circuits. [PDF]

Discov Nano
Hsieh YC, Lin YC, Huang YH, Chih YD, Chang J, Lin CJ, King YC.   +6 more
europepmc   +1 more source

A Review of Tunnel Field-Effect Transistors: Materials, Structures, and Applications. [PDF]

Micromachines (Basel)
Chen S, An Y, Wang S, Liu H.
europepmc   +1 more source

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Improved digital performance of charge plasma based junctionless C-FinFETs at 10 nm technology node and beyond

AEU - International Journal of Electronics and Communications, 2020
Abstract This paper investigates the digital performance of novel charge plasma based complementary (CPJL) FinFET inverters in terms of low and high noise margins, logic swing LS, DC power consumption PDC, rise tr and fall tf times, and propagations delay at both 10 and 7 nm technology nodes. In addition, their performance is compared with equivalent
Kallolini Banerjee, Abhijit Biswas
openaire   +1 more source

Effects of Fin Height on Digital Performance of Hybrid p-Si/n-InGaAs C-FinFETs at 25 nm Gate Length

2020
We report effects of Fin height on the logic application of hybrid complementary FinFETs (HC-Fins) composed of n-FinFETs and p-FinFETs employing InGaAs and Si channel, respectively, at gate length of 25 nm. Using extensive numerical analysis, we calculate rise time tr and fall time tf of NAND gate based inverter built with HC-Fins.
Kallolini Banerjee, Abhijit Biswas
openaire   +1 more source

Enhanced analog/RF performance of hybrid charge plasma based junctionless C-FinFET amplifiers at 10 nm technology node

Microelectronics Journal, 2023
Kallolini Banerjee, Abhijit Biswas
openaire   +1 more source