Results 91 to 100 of about 10,343 (214)
Performance Evaluation of Gate-Driven and Body-Driven MOS-Based Transimpedance Amplifiers [PDF]
Port Said Engineering Research JournalIn this paper, a comparative examination of four various transimpedance amplifier (TIA) topologies is performed. Each of the four topologies is precisely designed to fit a diverse range of applications. The discussed topologies are the common source (CS)
Aya Shaban +3 more
doaj +1 more source
1.25 Gbit/s ITU-T G.984.2 burst-mode transimpedance amplifier without reset pins [PDF]
, 2007 A
Bauwelinck, Johan +6 more
core +2 more sources
Optimizing Analog Circuit Design Through a Machine Learning‐Assisted Evolutionary Algorithm
Electronics Letters, Volume 61, Issue 1, January/December 2025.This work presents an improved and efficient machine learning‐assisted evolutionary algorithm for analogue circuit sizing. The proposed approach integrates a machine learning model into the evolutionary algorithm optimization process, effectively reducing the number of required simulations and improving the convergence speed.
Yu‐Yu Chen, Shao‐Yun Fang
wiley +1 more source
Design of a Broadband Amplifier for High Speed Applications [PDF]
, 2002 This paper provides comprehensive insight into the design approach followed for an amplifier dedicated to high speed base band signals. To demonstrate the methodology, an amplifier consisting of nine PHEMT cascode cells within a distributed amplifier ...
Camargo, E. +4 more
core +1 more source
A Low Power, High Input Dynamic Range and High Precision Current‐Mode Loser‐Take‐All Circuit
Electronics Letters, Volume 61, Issue 1, January/December 2025.This letter a novel current‐mode loser‐take‐all circuit for a wide range of inputs. The proposed circuit has been designed and simulated in 180 nm CMOS technology. The results confirm that the maximum error has been reduced over a wide range of input comparing the other similar works.
Bashir Makki Jebur +3 more
wiley +1 more source
14-bit 2.2-MS/s sigma-delta ADC's [PDF]
, 2000 This paper presents the design and test results of a fourth-order and sixth-order 14-bit 2.2-MS/s sigma-delta analog-to-digital converter (ADC). The analog modulator and digital decimator sections were implemented in a 0.35 μm CMOS double-poly triple ...
Geddie, C et al +3 more
core +2 more sources
ReCIM: A SRAM‐Based Digital–Analogue Hybrid CIM Reformer Accelerator Macro
Electronics Letters, Volume 61, Issue 1, January/December 2025.In this study, we introduce a SRAM‐based digital‐analogue hybrid reformer computing‐in‐memory accelerator macro. This macro presents an absolute maximum value addressing circuit which facilitates the hash bucketing process and enables the utilisation of strongly‐correlated (S‐C) vectors for attention mechanism computations, thereby improving ...
Yu Liu +7 more
wiley +1 more source
A Structural Offset Suppression Technique for Single‐Ended Hybrid ΣΔ CDCs
Electronics Letters, Volume 61, Issue 1, January/December 2025.This article presents an offset cancellation technique for single‐ended hybrid continuous‐time/discrete‐time (CT/DT) ΣΔ current‐to‐digital converters (CDCs). An auxiliary amplifier is introduced in the main amplifier's output branch to suppress structural offset caused by integration node clamping. Simulation results show a 20 dB reduction in DC offset
Yinuo Chen +3 more
wiley +1 more source
Designing analog circuits in CMOS [PDF]
, 2004 The evolution in CMOS technology dictated by Moore's Law is clearly beneficial for designers of digital circuits, but it presents difficult challenges, such as lowered nominal supply voltages, for their peers in the analog world who want to keep pace ...
Annema, Anne-Johan +3 more
core +1 more source
IEEE AccessIn this study, an extended cascode structure is proposed to enhance the output power of a K-band CMOS power amplifier. The extended cascode structure can increase supply voltage by additionally stacking a common-gate (CG) transistor in the typical ...
Hayeon Jeong, Changkun Park
doaj +1 more source