Results 241 to 250 of about 51,131 (290)

The Future of Charge Trapping Memories

2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2007
Floating gate memory cells running into scaling limitations caused by reduced gate coupling and excessive floating gate interference, charge trapping in its two variants multi bit charge trapping and charge trapping NAND is the most promising technology for the mid term.
T. Mikolajick, M. Specht, N. Nagel, T. Mueller, S. Riedel, F. Beug, T. Melde, K.-H. Kusters   +7 more
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Future trends in charge trapping memories

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, 2006
Charge trapping memories offer advantages for scaling data flash memories in the sub 50nm groundrule. This paper reviews the progress of the main concepts in charge trapping, NROM and SONOS. Both have undergone significant new developments, like the 4 bits/cell for the NROM and the introduction of new materials for SONOS and new cell structures, e.g ...
K.-H. Kuesters, C. Ludwig, T. Mikolajick, N. Nagel, M. Specht, V. Pissors, N. Schulze, E. Stein, J. Willer   +8 more
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Effect of trapped charge accumulation on the retention of charge trapping memory

Journal of Semiconductors, 2010
The accumulation process of trapped charges in a TANOS cell during P/E cycling is investigated via numerical simulation. The recombination process between trapped charges is an important issue on the retention of charge trapping memory. Our results show that accumulated trapped holes during P/E cycling can have an influence on retention, and the ...
Rui Jin, Xiaoyan Liu, Gang Du, Jinfeng Kang, Ruqi Han   +4 more
openaire   +1 more source

Graphene-quantum-dot nonvolatile charge-trap flash memories

Nanotechnology, 2014
Nonvolatile flash-memory capacitors containing graphene quantum dots (GQDs) of 6, 12, and 27 nm average sizes (d) between SiO2 layers for use as charge traps have been prepared by sequential processes: ion-beam sputtering deposition (IBSD) of 10 nm SiO2 on a p-type wafer, spin-coating of GQDs on the SiO2 layer, and IBSD of 20 nm SiO2 on the GQD layer ...
Soong, Sin Joo, Jungkil, Kim, Soo Seok, Kang, Sung, Kim, Suk-Ho, Choi, Sung Won, Hwang   +5 more
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Al2O3–Cu2O composite charge-trapping nonvolatile memory

Journal of Materials Science: Materials in Electronics, 2016
In this work, we have fabricated and thoroughly characterized dielectric-stacked memory devices with Al2O3–Cu2O composites as the charge trapping layer which are prepared by using atomic layer deposition and RF-magnetron sputtering techniques. The devices exhibit a large memory window of 13.27 V and a density of the trapped charges of 9.37 × 1012 cm−2 ...
Jinqiu Liu, Jianxin Lu, Bo Xu, Yidong Xia, Jiang Yin, Zhiguo Liu   +5 more
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Advancement in Charge-Trap Flash memory technology

2013 5th IEEE International Memory Workshop, 2013
Charge-trap Flash memory has been successfully productized in high volume for several technology generations. Two-bits-per-cell MirrorBit® charge-trap technology has been the industry benchmark for NOR Flash for more than a decade, spanning six generations of scaling.
Saied Tehrani, James Pak, Mark Randolph, Yu Sun, Sameer Haddad, Eduardo Maayan, Yoram Betser   +6 more
openaire   +1 more source

New nonvolatile memory with charge-trapping sidewall

IEEE Electron Device Letters, 2003
This letter reports on the development of a new nonvolatile memory with charge-trapping sidewalls using sub-0.1-/spl mu/m MOSFET technology. This memory has silicon nitride (SiN) sidewalls at both sides of the gate to store the charge. We have found that optimization of the p-n junction edge with the sidewall enables writing, reading, and erasing a 2 ...
M. Fukuda, T. Nakanishi, Y. Nara
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A TiAl2O5 nanocrystal charge trap memory device

Applied Physics Letters, 2010
A charge trapping memory device using Ti0.2Al0.8Ox film as charge trapping layer and amorphous Al2O3 as the tunneling and blocking layers was fabricated for nonvolatile memory application. TiAl2O5 nanocrystals are precipitated from the phase separation of Ti0.2Al0.8Ox film annealed at 900 °C.
Yue Zhou, Jiang Yin, Hanni Xu, Yidong Xia, Zhiguo Liu, Aidong Li, Youpin Gong, Lin Pu, Feng Yan, Yi Shi   +9 more
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Recent advances in charge trap flash memories

2009 2nd International Workshop on Electron Devices and Semiconductor Technology, 2009
This paper reviews recent advances in Charge Trap Flash (CTF) memories. CTFs are predicted to replace the traditional floating-gate flash devices beyond the 32 nm node. The paper focuses on work done at IIT Bombay in the areas of both nitride-based SONOS devices as well as nanocrystal (NC)-based devices.
C. Sandhya, P. K. Singh, S. Gupta, H. Rohra, M. Shivatheja, U. Ganguly, R. Hofmann, G. Mukhopadhyay, S. Mahapatra, J. Vasi   +9 more
openaire   +1 more source

HfTiON as Charge-Trapping Layer for Nonvolatile Memory Applications

ECS Meeting Abstracts, 2012
Abstract not Available.
Lai, PT, HUANG, X
openaire   +3 more sources