Results 251 to 260 of about 51,131 (290)

BaTiO3 as charge-trapping layer for nonvolatile memory applications

Solid-State Electronics, 2013
The charge-trapping (CT) properties of BaTiO3 are investigated by using an Al/Al2O3/BaTiO3/SiO2/Si structure. The memory device with BaTiO3 as CT layer shows promising performance in terms of large memory window (8.6 V by ±12 V for 1 s), high program speed with low gate voltage (a VFB shift of 2.9 V at +6 V, 100 μs), negligible VFB shift after 105 ...
Huang, X.D., Sin, Johnny K.O., Lai, P.T.
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3D Charge Trap NAND Flash Memories

2016
This chapter starts off with 2 vertical channel architectures named BiCS (Bit Cost Scalable) and P-BiCS (Pipe-Shaped BiCS), respectively. BiCS was proposed for the first time by Toshiba in 2007, and another version called P-BiCS was presented in 2009 to improve retention, source selector performances and source line resistance.
Luca Crippa, Rino Micheloni
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High performance charge-trapping flash memory with highly-scaled trapping layer

2011 11th Annual Non-Volatile Memory Technology Symposium Proceeding, 2011
We report a novel charge-trapping (CT) flash memory device with highly scaled equivalent-Si 3 N 4 -thickness (ENT) trapping layer
Albert Chin, C. Y. Tsai, Hong Wang
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“Solid state charge trapping”: Examples of polymer systems showing memory effect

Journal of Electroanalytical Chemistry, 2007
The paper reports on a characteristic property of electroactive materials bearing an electron-rich and an electron-poor moiety, known as charge trapping. As examples of materials that exhibit this phenomenon, films of poly(4,4 ''-dipentoxy-4 '-(2,2 '-dicyano)ethenyl-2,2 ':5 ',2 ''-terthiophene), poly(2,3-dihexylthieno[3,4-b]pyrazine) and a blend ...
Casalbore-Miceli, G., Camaioni, N., Geri, A., Ridolfi, G., Zanelli, A., Gallazzi, M.C., Maggini, M., Benicori, T.   +15 more
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Investigation of vertically trapped charge locations in Cr-doped-SrTiO3-based charge trapping memory devices

Journal of Applied Physics, 2012
In this paper, vertically trapped charge location is investigated to understand the carrier-transport dynamics in chromium-doped strontium titanate (Cr-SrTiO3 (STO))-based charge trapping memory devices using a transient analysis method. The vertical location of trapped charges is found to move from the Cr-SrTiO3/Si3N4 interface to the bulk region of ...
Yujeong Seo, Min Yeong Song, Ho-Myoung An, Yeon Soo Kim, Bae Ho Park, Tae Geun Kim   +5 more
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Investigation of charge trap and loss characteristics for charge trap memory by electrostatic force microscopy

2011 11th Annual Non-Volatile Memory Technology Symposium Proceeding, 2011
In this work, we employ the electrostatic force microscopy (EFM) technique to investigate the charge trapping and loss properties of Hf-based trapping structures by contact potential differences (CPDs) measurement. For different samples, the electron densities after injection and after 2 hours retention time are extracted from the measured CPDs.
Chenxin Zhu, Rong Yang, Zongliang Huo, Zhongguang Xu, Dongxia Shi, Jing Liu, Guangyu Zhang, Ming Liu   +7 more
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Optical capacitance-voltage characterization of charge traps in the trapping nitride layer of charge trapped flash memory devices

Applied Physics Letters, 2007
Extracting the trap distribution in charge trapping layers of charge trap flash memory devices, an optical C-V method (OCVM) is proposed. Applying photons with λ=532nm to the oxide-nitride-oxide layer with 50∕60∕23Å in metal-oxide-nitride-oxide-semiconductor charge trap flash devices, the trap density in the charge trapping nitride layer is extracted ...
Jang Uk. Lee, Kang Seob Roh, Gu Cheol Kang, Seung Hwan Seo, Kwan Young Kim, Sunyeong Lee, Kwan Jae Song, Chang Min Choi, So Ra Park, Jun Hyun Park, Ki Chan Jeon, Dae Hwan Kim, Byung-Gook Park, Jong Duk Lee, Dong Myong Kim   +14 more
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Local accumulated free carriers in charge trapping memory

2008 IEEE Silicon Nanoelectronics Workshop, 2008
The effects of local accumulated free carriers on CTM cell's performance are investigated by numerical simulation. Simulation results indicates that local accumulated free carriers do not affect programming and erasing characteristic, however, they are important to CTM's retention characteristic, especially in low threshold state.
Y.C. Song, X. Y. Liu, K. Zhao, J.F. Kang, R.Q Hant, Z.L. Xia, D. Kim, K-H Lee   +7 more
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Charge-Trap Transistors for CMOS-Only Analog Memory

IEEE Transactions on Electron Devices, 2019
Since our demonstration of unsupervised learning using the CMOS-only charge-trap transistors (CTTs) as analog synapses, there has been an increasing interest in exploiting the device for various other neural network (NN) applications. However, most of these studies are limited to mere simulation due to the absence of detailed experimental device ...
Xuefeng Gu, Zhe Wan, Subramanian S. Iyer
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Novel Device Structures for Charge Trap Flash Memories

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, 2006
Demands for the high-density non-volatile memory products have been growing explosively. For further scaling of flash memory devices, however, the currently-dominant poly-silicon floating gate structures show several limitations, and novel structures based on charge traps are emerging as a strong contender. We present nanoscale charge trap flash memory
Byung-gook Park, Il Park, Jung-hoon Lee, Byung Choi   +3 more
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