Results 261 to 270 of about 51,131 (290)

Simulation of charge trapping memory with novel structures

2008 9th International Conference on Solid-State and Integrated-Circuit Technology, 2008
The floating gate type of flash memory is impossible to scale down to beyond 45 nm due to the difficulty in scaling the tunnel oxide and the gate coupling ratio. Because of the difficulty in maintaining high gate coupling ratio and preventing cross talk between neighboring cells, NAND technology is forecasted to migrate gradually from floating gate ...
X. Y. Liu, Y. C. Song, null Gang Du, R.Q. Han, Z. L. Xia, D. Kim, K.-H. Lee   +6 more
openaire   +1 more source

Charge trapping and device behavior in ferroelectric memories

Applied Physics Letters, 1996
The electric field emanating from the surface of a poled ferroelectric (FE) can control the conduction properties of an overlying semiconducting (SC) film; this combination of materials can thus serve as a nondestructive readout (NDRO), nonvolatile memory device.
C. H. Seager, D. C. McIntyre, W. L. Warren, B. A. Tuttle   +3 more
openaire   +1 more source

Simulation on endurance characteristic of charge trapping memory

2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2013
A comprehensive simulation method for endurance reliability issues in charge trapping memory is developed. For this purpose, a practical algorithm is carefully designed to investigate the cycling performance of charge trapping memory. The models that account for the generation of substrate/tunneling oxide interface trapped charge and oxide trapped ...
Zhiyuan Lun, Taihuan Wang, Lang Zeng, Kai Zhao, Xiaoyan Liu, Yi Wang, Jinfeng Kang, Gang Du   +7 more
openaire   +1 more source

(Invited) Charge Trapping Type SOI-FinFET Flash Memory

ECS Meeting Abstracts, 2014
Y. X. Liu, T. Matsukawa, K. Endo, S. O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, W. Mizubayashi, Y. Morita, S. Migita, H. Ota, and M. Masahara National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba Central 2, 1-1-1 Umezono, Tsukuba-shi, Ibaraki 305-8568, Japan.
Yongxun Liu, T Nabatame, T Matsukawa, K Endo, S O'uchi, J Tsukada, H Yamauchi, Y Ishikawa, W Mizubayashi, Y Morita, S Migita, H Ota, T Chikyow, M Masahara   +13 more
openaire   +1 more source

Anomalous Erase Behavior in Charge Trapping Memory Cells

2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, 2008
This article details an anomalous erase behavior in charge trapping memory devices which is visible in a characteristic erase hump in transient erase curves. For an initial period of time a Vt increase is seen when erase condition are applied to virgin cells before the expected erasing takes place for longer erase pulse duration.
M. F. Beug, T. Melde, M. Isler, L. Bach, M. Ackermann, S. Riedel, K. Knobloch, C. Ludwig   +7 more
openaire   +1 more source

Charge Loss Mechanisms of Nitride-Based Charge Trap Flash Memory Devices

IEEE Transactions on Electron Devices, 2013
Technology scaling challenges for flash memory beyond 30 nm exacerbated as device fundamental limits are fast approaching. Nitride-based charge trap flash (CTF) is one of the most viable alternatives to eclipse floating gate flash in the market by leveraging the existing materials as compared with other exploratory nonvolatile memory devices.
Meng Chuan Lee, Hin Yong Wong
openaire   +1 more source

Overview of charge trapping memory devices—charge trapping layer engineering

2020
Ammar Nayfeh, Nazek El-Atab
openaire   +1 more source

Long‐Term Retention of Low‐Power, Nonvolatile Organic Transistor Memory Based on Ultrathin, Trilayered Dielectric Containing Charge Trapping Functionality

Advanced Functional Materials, 2020
Junhwan Choi, Min Ju Kim, Byung Jin Cho
exaly  

Junctionless Based Charge Trapping Memory for Neuromorphic Applications

Extended Abstracts of the 2022 International Conference on Solid State Devices and Materials, 2022
Md. Hasan Ansari, Nazek El Atab
openaire   +1 more source

Charge-trapping MOS memory structure using anodic alumina charging medium

Microelectronic Engineering, 2011
E. Hourdakis, A.G. Nassiopoulou
openaire   +1 more source