Results 251 to 260 of about 363,591 (305)
Some of the next articles are maybe not open access.
Science, 1981
The cell division cycle of both mammalian cells and microorganisms, which apparently has both deterministic and probabilistic features, is a clock of sorts in that the sequence of events that comprise it measures time under a given set of environmental conditions.
L N, Edmunds, K J, Adams
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The cell division cycle of both mammalian cells and microorganisms, which apparently has both deterministic and probabilistic features, is a clock of sorts in that the sequence of events that comprise it measures time under a given set of environmental conditions.
L N, Edmunds, K J, Adams
openaire +2 more sources
Circadian clock and cell cycle: Cancer and chronotherapy
Acta Histochemica, 2021The circadian clock is an endogenous timing system that ensures that various physiological processes have nearly 24 h circadian rhythms, including cell metabolism, division, apoptosis, and tumor production. In addition, results from animal models and molecular studies underscore emerging links between the cell cycle and the circadian clock.
Jing, Yao +4 more
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IEEE Journal of Solid-State Circuits, 2000
A 1.3-cycle lock-in time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation is proposed with an array structure of short-circuit-current-suppression interpolators. The circuits have been fabricated with a 0.25-/spl mu/m digital CMOS and operated in any condition where digital CMOS circuits operate.
T. Saeki +3 more
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A 1.3-cycle lock-in time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation is proposed with an array structure of short-circuit-current-suppression interpolators. The circuits have been fabricated with a 0.25-/spl mu/m digital CMOS and operated in any condition where digital CMOS circuits operate.
T. Saeki +3 more
openaire +1 more source
Cycling transcripts and the circadian clock
Current Biology, 1991Abstract Several animal and plant transcripts exhibit daily fluctuations in their abundance, and some of these gene products encode functions that may be very close to ‘central pacemaker ...
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Clock buffer with duty cycle corrector
Microelectronics Journal, 2010A clock buffer with duty cycle corrector circuit is presented. The proposed circuit can generate either 50% duty cycle or conserve the duty cycle as input clock. It corrects the input duty cycle of 10-90% for generated 50% duty cycle of output clock with error less than 0.9%.
Shao-Ku Kao, Yong-De You
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2001
Stochastic Local Search (SLS) methods have proven to be successful for solving propositional satisfiability problems (SAT). In this paper, we show a hardware implementation of the greedy local search procedure GSAT. With the use of field programmable gate arrays (FPGAs), our implementation achieves one flip per clock cycle by exploiting maximal ...
Martin Henz, Edgar Tan, Roland Yap
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Stochastic Local Search (SLS) methods have proven to be successful for solving propositional satisfiability problems (SAT). In this paper, we show a hardware implementation of the greedy local search procedure GSAT. With the use of field programmable gate arrays (FPGAs), our implementation achieves one flip per clock cycle by exploiting maximal ...
Martin Henz, Edgar Tan, Roland Yap
openaire +1 more source