Results 261 to 270 of about 363,591 (305)

A novel clock duty cycle stabilizer

2014 IEEE International Conference on Electron Devices and Solid-State Circuits, 2014
As ADCs improve to higher speed and resolution, A clock duty cycle stabilizer becomes more and more important. Improvement has been made in the proposed a clock duty cycle stabilizer circuit: a newly dynamic phase detector is designed to kill the dead working region; delay-limited cells are used to avoid false locking.
null Xiaofeng Shen, null Xingfa Huang
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Clocked Cell Cycle Clocks: Implications Toward Chronopharmacology and Aging

1978
Cell developmental and division cycles, comprising relatively discrete morphological and biochemical events that may be ordered sequentially or in a branching network, constitute “clocks” themselves in a general sense. Yet abundant evidence exists in both unicellular protistan and algal populations and in cultured mammalian cells that the cell division
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Clocked Cell Cycle Clocks: Ultradian, Circadian, and Infradian Interfaces

1981
The cell division cycle (cdc) of a typical microorganism such as Euglena comprises a series of relatively discrete morphological and biochemical events, and in a sense, the cdc is a time-measuring device, or “clock” (see Edmunds 1978). The attempts to describe the cell division cycle (cdc) fall into two broad categories: deterministic and in ...
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A 1.3 cycle lock time, non-PLL/DLL jitter suppression clock multiplier based on direct clock cycle interpolation for "clock on demand"

2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056), 2002
A 1.3-cycle lock time, jitter suppression clock multiplier based on direct clock cycle interpolation uses an array of short-circuit-current-suppression interpolators. The circuits are verified in 622 MHz clock and data recovery satisfying the ITU-T G.958 jitter tolerance specification.
T. Saeki, M. Mitsuishi, H. Iwaki, M. Tagishi   +3 more
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Low area pipelined circuits by multi-clock cycle paths and clock scheduling

Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06, 2006
A new algorithm is proposed to reduce the number of intermediate registers of a pipelined circuit using a combination of multi-clock cycle paths and clock scheduling. The algorithm analyzes the pipelined circuit and determines the intermediate registers that can be removed.
B.A. Rosdi, A. Takahashi
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A probabilistic approach to clock cycle prediction

Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems - TAU '02, 2002
When developing new technologies, it is important to have an indication of the gain that can be achieved by exploring different research directions. Part of this gain is measured by achievable system performance. In this paper, we focus on the a priori prediction of clock speed as a measure for system performance.Previous approaches to clock cycle ...
J. Dambre, D. Stroobandt, J. Van Campenhout   +2 more
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Sleep Cycle alarm clock

Nursing Children and Young People, 2017
Kirsten Huby, Joanna Smith
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Linking the Clock and the Cell Cycle

Science's STKE, 2006
The circadian clock is linked to the cell cycle in ways that are not clear. Pregueiro et al. investigated the relation between these two fundamental cellular processes in the fungus Neurospora .
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Cell cycle control in cancer

Nature Reviews Molecular Cell Biology, 2021
Helen K Matthews, Cosetta Bertoli, Robertus A M De Bruin   +2 more
exaly  

The marine nitrogen cycle: new developments and global change

Nature Reviews Microbiology, 2022
David A Hutchins, Douglas G Capone
exaly