Results 11 to 20 of about 34,539 (304)
Reconfigurable design with clock gating [PDF]
2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, 2008 This paper describes an approach for developing energy-optimized run-time reconfigurable designs which benefit from clock gating. The approach is applied to two techniques: multiplexer-based reconfiguration, and reconfigurable word-length optimization.
W.G. Osborne +3 more
openaire +1 more source
Robust, coherent, and synchronized circadian clock-controlled oscillations along Anabaena filaments
eLife, 2021 Circadian clocks display remarkable reliability despite significant stochasticity in biomolecular reactions. We study the dynamics of a circadian clock-controlled gene at the individual cell level in Anabaena sp.
Rinat Arbel-Goren +9 more
doaj +1 more source
Implementation of Clock Gating for Power Optimizing in Synchronous Design
Tikrit Journal of Engineering Sciences, 2018 Huffman coding is very important technique in information theory. Compression technique is the technology for reducing the amount of data used to denote any content without decreasing the quality.
Hussein Shakor Mogheer +1 more
doaj +3 more sources
Power Optimization For Multi-Core Memory Controller Using Intelligent Clock Gating Technique [PDF]
Journal of Electrical and Electronics Engineering, 2022 The demand for low-power digital systems is increasing daily, especially for the multi-core design on SoC. Different IP cores of the existing multi-core memory controller need to communicate to achieve specific tasks on the same die.
NOAMI Ahmed +2 more
doaj
eLife, 2021 Adverse early-life exposures have a lasting negative impact on health. Neonatal hyperoxia that is a risk factor for bronchopulmonary dysplasia confers susceptibility to influenza A virus (IAV) infection later in life. Given our previous findings that the
Yasmine Issah +11 more
doaj +1 more source
Vector processing-aware advanced clock-gating techniques for low-power fused multiply-add [PDF]
, 2018 The need for power efficiency is driving a rethink of design decisions in processor architectures. While vector processors succeeded in the high-performance market in the past, they need a retailoring for the mobile market that they are entering now ...
Cristal Kestelman, Adrián +5 more
core +2 more sources
A power-efficient pipeline based clock gating FIFO for a dual ported memory array [PDF]
Songklanakarin Journal of Science and Technology (SJST), 2023 A FIFO is a special type of buffer that controls the data flow between the sender and receiver. It is used to monitor the serial data flow and to avoid mismatch conditions.
S. Dhanasekar +3 more
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CMOS Technology for Increasing Efficiency of Clock Gating Techniques Using Tri-State Buffer
Walailak Journal of Science and Technology, 2016 Clock gating is an effective technique of decreasing dynamic power dissipation in synchronous design. One of the methods used to realize this goal is to mask the clock which goes to the unnecessary to use in specific time.
Maan HAMEED +3 more
doaj +1 more source
Feto-Maternal Crosstalk in the Development of the Circadian Clock System
Frontiers in Neuroscience, 2021 The circadian (24 h) clock system adapts physiology and behavior to daily recurring changes in the environment. Compared to the extensive knowledge assembled over the last decades on the circadian system in adults, its regulation and function during ...
Mariana Astiz, Henrik Oster
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A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory Design [PDF]
, 2008 This paper presents a novel design of address pointer for FIFO memory circuits. Advantages of the proposed design include: reduced capacitive load on the pointer clock path, the use of a true single-phase clock, and double- edge-triggering clock scheme ...
Ramamoorthy, Saravanan +2 more
core +2 more sources