Results 21 to 30 of about 227,711 (205)
Immunity of coherent stroboscopic processing system of ultra wideband signals during synchronous mode [PDF]
ITM Web of Conferences, 2019 Analyze of the radio pulse stroboscopic schema work in “synchronous” mode was made at clock interval synchronization by the second harmonic of intermediate frequency.
Pak Oleg, Zakharchenko Vladimir
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Design of a Highly Robust Triple-Node-Upset Self-Recoverable Latch
IEEE Access, 2021 Due to semiconductor technology scaling, integrated circuits have become more sensitive to soft errors. To effectively tolerate multi-node-upsets caused by soft errors and reduce the power dissipation and delay of a latch, this paper proposes a novel ...
Hui Xu +4 more
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ITEGAM-JETIAClock distribution contributes significantly to the dynamic power consumption of contemporary embedded processors, especially in low-power 32-bit RISC-V cores.
Himabindhu Jala, Karimullah Shaik
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A variation tolerant data dependent clock gating approach for PSN attenuated low power digital IC
Ain Shams Engineering Journal, 2019 The evolution of semiconductor industry has brought in high current flow across the power rails (‘Vdd’ and ground) of digital integrated circuits (IC) encapsulated by the modern chip packages. This instigates the uncontrollable generation of Power Supply
Pritam Bhattacharjee +2 more
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Clock Gating Assertion Check An Approach Towards Efficient Verification Closure On Clock Gating Functionality [PDF]
, 2017 One of the power reduction techniques widely used in Register Transfer Level (RTL) stage of a design is clock gating. However, the addition of clock gating logics has increased the complexity of a design and therefore considerable amount of verification ...
Wang, Jian Zhong
core +1 more source
VLSI Synthesis for Low-Power Clocking in Synchronous Designs
Iraqi Journal of Industrial ResearchIn the field of information theory, the significance of low-power techniques cannot be overstated. Among these, clock gating stands out as a potent method to mitigate power dissipation in synchronous designs.
Naseer Alwan Hussein +2 more
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Data-Driven Clock Gating for Digital Filters
, 2010 Digital filters implement a continuos computation and therefore generally they do not exhibit any structural idleness. This can prevent the usage of classical low-power optimizations that exploit idleness, such as clock gating. In this work, we propose a
Alberto Bocca +9 more
core +1 more source
Placement-aware clustering for integrated clock and power gating
, 2009 Clock-gating and power-gating are the most widely used solutions for reducing dynamic and static power. They can be potentially integrated so that clock-gating conditions can be used to control the power-gating circuitry thus also reducing static power ...
Andrea Calimera +10 more
core +1 more source
Scheme features of radio pulse gating for radar measurements [PDF]
ITM Web of Conferences, 2019 The model of a radio pulse stroboscopic converter consisting of a mixer and a narrowband filter tuned to the difference frequency of the carrier signals is considered. We demonstrate that the measurement of the phase structure of the input signals can be
Zakharchenko Vladimir +1 more
doaj +1 more source
FEBS Letters, EarlyView.Mycobacterial 3‐methylcrotonyl‐CoA carboxylase uses a mobile biotin‐carrying domain to shuttle a carboxyl group between two catalytic sites, enabling carboxylation of 3‐methylcrotonyl‐CoA during leucine breakdown. Cryo‐electron microscopy captures the carrier at both sites and reveals an inward loop movement that may prevent futile rebinding to the ...
Ajit Yadav +2 more
wiley +1 more source