Results 71 to 80 of about 1,394 (169)

Performance Analysis of GAA-CNTFET and TG-CNTFET Considering Source-to-Drain Tunneling for SRAM Bit-Cell Optimization

This manuscript presents a comprehensive performance comparison between Gate-All-Around Carbon Nanotube Field-Effect Transistors (GAA-CNTFETs) and Top-Gate CNTFETs (TG-CNTFETs) at a 10 nm technology node.
Ashish Sachdeva, Priyanka Bansal, Shaminder Kaur, Appikatla Phani Kumar, Shaik Javid Basha, Geetanjali Singla   +5 more
core   +1 more source

Topological failure mode taxonomy and variation-aware design space exploration of carbon nanotube field-effect transistor flip-flops under process-induced geometric perturbations

Scientific Reports
Carbon Nanotube Field-Effect Transistors (CNTFETs) represent a promising post-CMOS technology, yet their adoption in sequential logic remains hindered by device-level non-idealities.
M. Chandana, Owais Ahmad Shah, Vakkalakula Bharath Sreenivasulu   +2 more
doaj   +1 more source

Synaptic Characteristics of Fully Depleted Silicon‐on‐Insulator Metal‐Oxide‐Semiconductor Field‐Effect Transistors and Synapse‐Neuron Arrayed Neuromorphic Hardware System

Advanced Intelligent Systems, Volume 6, Issue 6, June 2024.
Fully depleted silicon‐on‐insulator (FDSOI) field‐effect transistor (FET) is demonstrated as for artificial synapse, where FDSOI substrate mitigates leakage current and low power when compared to bulk Si. To validate stable hardware interactions, 5 × 6 synapse arrays using these verified FDSOI FETs are interconnected to 10 × 10 LIF neuron arrays.
Yu‐Rim Jeon, Jeong‐Hoon Kim, Deji Akinwande, Changhwan Choi   +3 more
wiley   +1 more source

A novel, efficient CNTFET Galois design as a basic ternary-valued logic field

, 2012
Peiman Keshavarzian1, Mahla Mohammad Mirzaee21Kerman Branch, Computer Engineering Department, Islamic Azad University, Kerman, Iran; 2Science and Research Branch, Computer Engineering Department, IA University, Kerman, IranAbstract: This paper presents ...
Mirzaee MM, Keshavarzian P
core  

Proposing Very Low Power Three-Valued Flip-Flops by Using CNTFET Transistors [PDF]

Iranian Journal of Electrical and Electronic Engineering
The scaling limitations of Complementary Metal-Oxide-Semiconductor (CMOS) transistors to achieve better performance have led to the attention of other structures to improve circuit performance. One of these structures is multi-valued circuits.
Amirhossein Salimi, Behzad Ebrahimi, Massoud Dousti   +2 more
doaj  

Fast Nitrogen Dioxide Sensing with Ultralow‐Power Nanotube Gas Sensors

Advanced Sensor Research, Volume 3, Issue 1, January 2024.
This work presents a fast and ultralow‐power NO2 sensor that uses an individual carbon nanotube as its sensing material. The study reports significantly improved recovery and readout times of 1–5 min and limit of detection below 10 ppb, while maintaining carbon nanotube's known advantage in power consumption (peak power below 10 microwatts).
Seoho Jung, Cosmin Roman, Christofer Hierold   +2 more
wiley   +1 more source

Impact of Temperature Variations on Design Parameters of CNTFET [PDF]

, 2021
In this paper we analyse the impact of temperature variations on design parameters of CNTFET with particular reference to the output and trans-characteristics, the output resistance, the transconductance and cut-off frequency.
Roberto Marani, Anna Gina Perri
core  

Sensitive Detection of a Gaseous Analyte with Low‐Power Metal–Organic Framework Functionalized Carbon Nanotube Transistors

Advanced Electronic Materials, Volume 10, Issue 1, January 2024.
Outstanding performance in detecting ethanol molecules at sub‐ppb concentrations is achieved by integrating large‐diameter carbon nanotube field‐effect transistors with a metal–organic framework layer. These sensors operate with extremely low power consumption in the picowatt range and exhibit insensitivity to ambient humidity conditions, positioning ...
Sandeep Kumar, Simone Dehm, Laura Wieland, Abhinav Chandresh, Lars Heinke, Benjamin S. Flavel, Ralph Krupke   +6 more
wiley   +1 more source

Energy Efficient CNTFET Based Full Adder Using Hybrid Logic [PDF]

, 2017
Full Adder is the basic element for arithmetic operations used in Very Large Scale Integrated (VLSI) circuits, therefore, optimization of 1-bit full adder cell improves the overall performance of electronic devices.
, Priya Kaushal, Rajesh Mehra
core   +1 more source

A LOW POWER AND AREA EFFICIENT CNTFET BASED GDI CELL FOR LOGIC CIRCUITS

, 2020
The main objectives for today's VLSI circuit designers are designing circuits which occupy less area, consume low power with improved performance. There has always been a tradeoff between these three factors while designing.
V T Sreedevi, P Reena Monica
core