Results 31 to 40 of about 118,732,585 (294)

A 0.6 V 4 GS/s −56.4 dB THD Voltage-to-Time Converter in 28 nm CMOS

open access: yesIEEE Access, 2022
A 0.6 V voltage-to-time converter (VTC) has been presented in this work for the emerging energy-efficient time-domain circuits and systems. The proposed VTC supports a rail-to-rail input by leveraging shrink sampling with two cascaded voltage sampling ...
Qian Chen, Chirn Chye Boon, Yuan Liang
doaj   +1 more source

High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip

open access: yesApplied Sciences, 2017
This paper presents the design and implementation of a new digital-to-time converter (DTC). The obtained resolution is 1.02 ps, and the dynamic range is about 590 ns. The experimental results indicate that the measured differential nonlinearity (DNL) and
Hai Wang, Min Zhang, Yan Liu
doaj   +1 more source

Design of Power/Analog/Digital Systems Through Mixed-Level Simulations [PDF]

open access: yes, 2011
In recent years the development of the applications in the field of telecommunications, data processing, control, renewable energy generation, consumer and automotive electronics determined the need for increasingly complex systems, also in shorter time ...
Coppola, Marino
core   +1 more source

A stochastic time-to-digital converter for digital phase-locked loops [PDF]

open access: yes
Digital phase-locked loops (PLLs) have been receiving increasing attention recently due to their ease of integration, scalability and performance comparable to their analog counterparts. In digital PLLs, increased resolution in time-to-digital conversion
Ok, Kerem
core   +4 more sources

3D Photon-To-Digital Converter for Radiation Instrumentation: Motivation and Future Works

open access: yesSensors, 2021
Analog and digital SiPMs have revolutionized the field of radiation instrumentation by replacing both avalanche photodiodes and photomultiplier tubes in many applications.
Jean-François Pratte   +9 more
doaj   +1 more source

A Hardware-Error-Aware Time-Domain CIM Accelerator for AdderNet with Significance-Aware Dual-Mode DTC Encoding and Shared-Clock TDC Readout

open access: yesApplied Sciences
Adder neural networks remove multiplication from convolution, yet their direct L1-distance datapath still requires subtraction, absolute-value generation, and wide accumulation. We address this cost by mapping the online L1 operation to minimum selection
Aoming Zhan   +3 more
doaj   +1 more source

A novel time to digital converter architecture for time of flight positron emission tomography

open access: yes, 2013
Positron emission tomography (PET) is a molecular imaging technique that provides images of physiological processes inside the body. In clinical applications, PET image quality benefits from the time of flight (TOF) feature.
Luca Fanucci   +11 more
core   +1 more source

A DTC-Based Snapshot ADPLL With Feedforward Fractional Spur Cancellation and Asynchronous Duty-Modulation Dithering DCO Achieving–71.6 dBc Fractional Spur in 65-nm CMOS Process

open access: yesIEEE Access
This paper presents a DTC-based snapshot all-digital phase-locked loop (ADPLL) that achieves robust fractional spur suppression and low phase noise with compact circuit implementation.
Kihoon Kwon   +13 more
doaj   +1 more source

Exercise Capacity, Physical Activity, Fatigue, and Neurocognitive Function in Adult Survivors of Childhood Acute Lymphoblastic Leukemia

open access: yesPediatric Blood &Cancer, EarlyView.
ABSTRACT Background Adult survivors of childhood acute lymphoblastic leukemia (ALL) are at risk of reduced exercise capacity, decreased physical activity levels, persistent fatigue, and neurocognitive deficits. The aim was to investigate exercise capacity and physical activity levels of adult survivors of childhood ALL and their associations with ...
Laura Jess   +5 more
wiley   +1 more source

Sensitive, Linear, Robust Current-To-Time Converter Circuit for Vehicle Automation Application

open access: yes, 2020
Voltage-to-time and current-to-time converters have been used in many recent works as a voltage-to-digital converter for artificial intelligence applications. In general, most of the previous designs use the current-starved technique or a capacitor-based
Kyuwon Ken Choi   +3 more
core   +1 more source

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