Results 21 to 30 of about 4,746 (161)
Extending locked range of digital phase-locked loop by prediction estimation of states
A method to extend locked range of the positive zero crossing detection digital phase-locked loop(ZC-DPLL) was proposed.The nonlinear dynamical model of phase error of a non-controlled DPLL is firstly built,linearation predic-tion estimation of phase ...
ZHAO Yi-bo1 +3 more
doaj +2 more sources
Experimental research of transient processes in firmware digital phase-locked loop
This article considers the experimental research of transient processes that occur in digital phase-locked loops (DPLL) after closing the feedback loop. Firmware implementation of DPLL device was made for this purpose.
А. П. Бондарев +1 more
doaj +1 more source
Sub-parts Control Parameter Fitting Method of VSC Based on RTDS
Voltage source converter (VSC) is the main power electronic components of wind power, photovoltaic and converter stations. It's control mode and parameter setting have important influence on system operation.
Peng XU +3 more
doaj +1 more source
Study on Digital Phase-Locked Loop for Grid-connected Power Electronic Device
As the grid-connected power electronic device has been widely applied, digital phase-locked loop (PLL) is becoming a key technology of such devices. An advanced digital SRF-PLL is applied based on the synchronous rotating reference frame, and the unified
WANG Baogui +3 more
doaj
Semidigital PLL Design for Low-Cost Low-Power Clock Generation
This paper describes recent semidigital architectures of the phase-locked loop (PLL) systems for low-cost low-power clock generation. With the absence of the time-to-digital converter (TDC), the semi-digital PLL (SDPLL) enables low-power linear phase ...
Ni Xu, Woogeun Rhee, Zhihua Wang
doaj +1 more source
Analog-digital systems of phase-locked loop
Considered the system digital phase-locked loop with a frequency synthesizer (the reference signal generator), implemented by analog circuits phase-locked.
S. A. Gankevich
doaj
Extended Lock Range Zero-Crossing Digital Phase-Locked Loop with Time Delay
The input frequency limit of the conventional zero-crossing digital phase-locked loop (ZCDPLL) is due to the operating time of the digital circuitry inside the feedback loop.
Nasir Qassim
doaj +2 more sources
The technical feasibility of developing an Internet of Things multi‐user communication system is evaluated based on a central digital multiband carrierless amplitude and phase transmitter, which broadcasts data on multiple channels for a number of low ...
Luís Rodrigues +3 more
doaj +1 more source
An Improved Single Phase-locked Loop Based on Synchronous Reference Frame
Accurate tracking of phase angle, frequency and amplitude of the utility voltage is essential to ensure correct operation of grid connected inverters. The commonly used single phase-locked loop(SPLL) has poor dynamic characteristics due to the problem of
TANG Jianyu +4 more
doaj
Phase noise and jitter modeling for fractional-N PLLs [PDF]
We present an analytical phase noise model for fractional-N phase-locked loops (PLL) with emphasis on integrated RF synthesizers in the GHz range. The noise of the crystal reference, the voltage-controlled oscillator (VCO), the loop filter, the charge ...
S. A. Osmany +3 more
doaj

