Results 31 to 40 of about 4,746 (161)

Digital phase-locked loops tracked by a relay sensor [PDF]

IEEE Transactions on Communications, 1999
An optimal algorithm is presented for tracking the phase of a slowly modulating signal by means of digital sampling of its sign. Error bounds and a numerical illustration are given.
Bonnet, C., Partington, J.R., Sorine, M.
openaire   +2 more sources

Optimum digital phase-locked loops

Electronics Letters, 1975
The optimum discrete filters to track phase and frequency steps in the presence of additive white Gaussian noise are derived, and are found to be equivalent to the baseband models of 1st- and 2nd-order digital phase-locked loops, respectively. Practical design parameters are presented.
A.J. Ruddell, A.M. Rosie
openaire   +1 more source

Design and Implementation of a Digital Phase Locked Loop for GPS Synchronization

Algerian Journal of Signals and Systems
In this paper, a Digital Phase-Locked Loop (DPLL) for GPS synchronization is designed, implemented and tested. It consists of a Phase Frequency Detector (PFD), an RC Low-Pass Filter (LPF), and a Relaxation Voltage Controlled Oscillator (VCO).
Mouloud CHALLAL, Abderrahmane OUADI, Hamid BENTARZI, Abderazak CHERFI , Omar SAIDI   +4 more
doaj   +1 more source

Data Driven Second Integral Sliding Mode Control for the Digital Phase-Locked Loop

IEEE Access
The high accuracy and flexibility of the digital phase-locked loop (DPLL) make it a versatile tool with a wide range of applications in modern sensor technology.
Haiqin Liu, Mingdong Hou, Guangye Li, Renming Yang, Yun Zhang   +4 more
doaj   +1 more source

Performance Analysis of Zero Crossing DPLL with Linearized Phase Detector

International Journal of Information and Communication Technology Research, 2009
This work introduces a new structure of Zero Crossing Digital Phase Locked Loop with Arc Sine block (ASZCDPLL) to linearize the phase difference detection, and enhance the loop performance.
Qassim Nasir, Saleh AI-Araji
doaj  

Comparing Digital Phase-Locked Loop and Kalman Filter for Clock Tracking in Ultrawideband Location System

Journal of Electrical and Computer Engineering, 2018
For timing and synchronization system, digital phase-locked loop (DPLL) and Kalman filter all have been widely used as the clock tracking and clock correction schemes for the similar structure and properties.
Qian Gao, Chong Shen, Kun Zhang
doaj   +1 more source

Development of portable orthogonal lock-in amplifier based on FPGA

Dianzi Jishu Yingyong, 2018
A portable orthogonal phase-locked amplifier for weak signal detection has been developed based on FPGA. First,the signal processing module receives the signal,does variable gain amplification on the signal and puts it through the power frequency noise ...
Xie Guihui, Zheng Xuchu, Zhao Tianming, Liu Zixu, Zhao Juan   +4 more
doaj   +1 more source

FPGA-Based Implementation of All-Digital QPSK Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood Frequency Estimator

International Journal of Reconfigurable Computing, 2014
This paper presents an efficient all digital carrier recovery loop (ADCRL) for quadrature phase shift keying (QPSK). The ADCRL combines classic closed-loop carrier recovery circuit, all digital Costas loop (ADCOL), with frequency feedward loop, maximum ...
Kaiyu Wang, Zhiming Song, Xianwei Qi, Qingxin Yan, Zhenan Tang   +4 more
doaj   +1 more source

A Digitalized Silicon Microgyroscope Based on Embedded FPGA

Sensors, 2012
This paper presents a novel digital miniaturization method for a prototype silicon micro-gyroscope (SMG) with the symmetrical and decoupled structure. The schematic blocks of the overall system consist of high precision analog front-end interface, high ...
Dunzhu Xia, Cheng Yu, Yuliang Wang
doaj   +1 more source

Theoretical Upper and Lower Limits for Normalized Bandwidth of Digital Phase-Locked Loop in GNSS Receivers. [PDF]

Sensors (Basel), 2023
Song YJ, Pany T, Won JH.
europepmc   +1 more source