Results 41 to 50 of about 4,746 (161)
Table-Based Adaptive Digital Phase-Locked Loop for GNSS Receivers Operating in Moon Exploration Missions. [PDF]
Sensors (Basel), 2022 Song YJ, Won JH.
europepmc +1 more source
Sensors, 2018 This paper presents a 612–1152 MHz Injection-Locked Frequency Multiplier (ILFM). The proposed ILFM is used to send an input signal to a receiver in only the I/Q mismatch calibration mode. Adopting a Phase-Locked Loop (PLL) to calibrate the receiver
SungJin Kim +10 more
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Synchronized state in networks of digital phase-locked loops
Proceedings of the 8th IEEE International NEWCAS Conference 2010, 2010 Clock distribution networks of synchronized oscillators are an alternative approach to classical tree-like clock distribution methods. Each node of the network may consist of a phase-locked loop (PLL) trying to match the phase of its neighbors. Then a network of independent oscillators takes the place of the centralized clock source, providing separate
Akre, Jean-Michel +3 more
openaire +2 more sources
A Background Jitter Calibration for ADCs Using TDC Phase Information From ADPLL
IEEE AccessThe phase noise, commonly known as jitter, in Phase-Locked Loops (PLLs) is conventionally perceived as a stochastic process, necessitating a degree of tolerance in downstream circuits such as Analog-to-Digital Converters (ADCs). This paper addresses this
Haoyang Shen +4 more
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FPGA implementation of impedance-compensated phase-locked loop for HVDC converters
The Journal of Engineering, 2018 The phase-locked loop (PLL) plays a key role in HVDC systems. Recently, a new type of PLL called the impedance-compensated phase-locked loop (IC-PLL) was introduced to compensate for the voltage drop across the AC network's Thevenin impedance, making the
Yue Yi +2 more
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DESIGN & IMPLEMENTATION OF FRACTIONAL – N FREQUENCY SYNTHESIZER
Journal of Engineering, 2006 This research involves design & implementation of fractional – N frequency synthesizer with the following specifications: Frequency range (2350– 2750) MHz,Step size (1 kHz), Switching time 8.9 μs, & phase noise @10 kHz = -115dBc & spurious -69 dBc The ...
Ali M. N. Hassan
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A study on high-performance single-phase phase-locked loop method based on synchronous sampling SDFT
机车电传动In the traction drive control system of electric locomotives and rolling stock, the grid-side converter obtains phase information through a phase-locked loop and carries out precise control.
CHEN Zhibo +4 more
doaj
Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques
IEEE Open Journal of the Solid-State Circuits SocietyThis article proposes an mm-wave fractional-N all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, consequently improving jitter at lower power ...
Teerachot Siriburanon +3 more
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The Hybrid Method for On-line Harmonic Analysis
Advances in Electrical and Computer Engineering, 2011 The novel hybrid method of the Discrete Fourier Transform (DFT) and the Enhanced Phase-Locked Loop (EPLL) has been presented. The original well-known methods and the Hybrid method have been analysed and tested in several simulations and experiments ...
KNEZEVIC, J. M., KATIC, V. A.
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A 42.7Gb/s Optical Receiver With Digital Clock and Data Recovery in 28nm CMOS
IEEE AccessThis paper presents a broadband optical receiver that employs multiple bandwidth extension techniques in analog front-end (AFE) and has efficient digital clock and data recovery (CDR). The AFE is implemented exclusively with inverter-based stages.
Hyungryul Kang +7 more
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