Results 71 to 80 of about 77,045 (305)
Low-Jitter Clock Multiplication: a Comparioson between PLLs and DLLs [PDF]
, 2002 This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume
Beek, Remco C.H. van de +3 more
core +2 more sources
Advanced Science, EarlyView.Tracing the evolution from structural regulation to multifunctional integration, this paper systematically analyzes modification strategies for carbon‐based electrodes. It evaluates how element doping, surface functionalization, and composite material design affect the electrode performance, and offers perspectives on future applications and challenges
Yunlei Wang +4 more
wiley +1 more source
Performance Analysis of Zero Crossing DPLL with Linearized Phase Detector
International Journal of Information and Communication Technology Research, 2009 This work introduces a new structure of Zero Crossing Digital Phase Locked Loop with Arc Sine block (ASZCDPLL) to linearize the phase difference detection, and enhance the loop performance.
Qassim Nasir, Saleh AI-Araji
doaj
International Journal of Reconfigurable Computing, 2014 This paper presents an efficient all digital carrier recovery loop (ADCRL) for quadrature phase shift keying (QPSK). The ADCRL combines classic closed-loop carrier recovery circuit, all digital Costas loop (ADCOL), with frequency feedward loop, maximum ...
Kaiyu Wang +4 more
doaj +1 more source
A Digitalized Silicon Microgyroscope Based on Embedded FPGA
Sensors, 2012 This paper presents a novel digital miniaturization method for a prototype silicon micro-gyroscope (SMG) with the symmetrical and decoupled structure. The schematic blocks of the overall system consist of high precision analog front-end interface, high ...
Dunzhu Xia, Cheng Yu, Yuliang Wang
doaj +1 more source
Effect of various features on the life cycle cost of the timing/synchronization subsystem of the DCS digital communications network [PDF]
, 1978 The effect on the life cycle cost of the timing subsystem was examined, when these optional features were included in various combinations. The features included mutual control, directed control, double-ended reference links, independence of clock error ...
Kimsey, D. B.
core +1 more source
Interlayer Dzyaloshinskii–Moriya Interaction in Synthetic Ferrimagnets for Spiking Neural Networks
Advanced Science, EarlyView.This work introduces a groundbreaking integration of asymmetric magnetic structures (synthetic ferrimagnets) and antisymmetric magnetic interaction (interlayer Dzyaloshinskii–Moriya interaction) for the first time. It addresses the critical challenge of IL‐DMI detection and shows the discovery of unprecedented analog‐like spin‐orbit torque switching ...
Shen Li +14 more
wiley +1 more source
Digital command system second-order subcarrier tracking performance [PDF]
Equations to determine tracking performance for second order, phase locked loop used for subcarrier synchronization on digital command ...
Holmes, J. K., Tegnelia, C. R.
core +1 more source
A Low Noise Sub-Sampling PLL in Which Divider Noise Is Eliminated and PD-CP Noise Is not multiplied by N^2 [PDF]
, 2009 This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP)that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied by N2
Bohsali, Mounhir +3 more
core +3 more sources
Advanced Science, EarlyView.Hydrogel‐based wearable electronics hold great promise for physiological monitoring in privacy‐sensitive regions. In this study, a polyurethane (PU) microfiber‐reinforced gelatin hydrogel e‐skin is developed, boasting multiple advantages such as ultra‐thinness, high toughness, and long‐term skin conformability.
Yarong Ding +11 more
wiley +1 more source