Results 81 to 90 of about 41,452,026 (246)
This paper presents a 612–1152 MHz Injection-Locked Frequency Multiplier (ILFM). The proposed ILFM is used to send an input signal to a receiver in only the I/Q mismatch calibration mode. Adopting a Phase-Locked Loop (PLL) to calibrate the receiver
SungJin Kim +10 more
doaj +1 more source
From Sensing Mechanisms to System Co‐Design: Graphene‐Based Sensors and Readout Circuits
This review establishes a unified PS–EQ–RF framework linking graphene sensing mechanisms, native electrical outputs, and output‐specific readout circuits. Voltage‐, current‐, resistance‐, and capacitance‐type sensing systems are systematically classified to guide architecture selection, low‐noise design, system co‐design, and practical integration ...
Jinduo Zhang +5 more
wiley +1 more source
FPGA implementation of impedance-compensated phase-locked loop for HVDC converters
The phase-locked loop (PLL) plays a key role in HVDC systems. Recently, a new type of PLL called the impedance-compensated phase-locked loop (IC-PLL) was introduced to compensate for the voltage drop across the AC network's Thevenin impedance, making the
Yue Yi +2 more
doaj +1 more source
A mechanically robust, self‐healable, moisturizing, cryotolerant and adhesive GelMA hydrogel is developed by incorporating polyvinyl alcohol, acrylic acid, sodium tetraborate, and glycerol into GelMA matrix via a photoinitiated polymerization process. The hydrogel‐derived omni‐healable ionotronic pressure sensor can sensitively and consistently monitor
Zhikang Li +16 more
wiley +1 more source
A carrier‐free zinc‐coordinated polyphenol nanoplatform (ZnCA NPs) is designed as an “all‐in‐one” therapeutic strategy for intestinal inflammation. The ZnCA NPs exhibit enhanced colonic accumulation and broad‐spectrum reactive oxygen and nitrogen species scavenging.
Qiwen Xie +7 more
wiley +1 more source
DESIGN AND MODELLING HILBERT TRANSFORM BASED PHASE DETECTOR FOR ALL DIGITAL PHASE LOCKED LOOP
The Phase Locked Loop (PLL) is an almost always used electronics circuit for communication systems like modulator, demodulator, frequency generator and frequency synthesizer etc. All-digital phase locked loop (ADPLL) is digital version of the PLL.
Anupama Patil*, Dr P.H.Tandel
core +1 more source
A digital implementation of a frequency steered phase locked loop [PDF]
A digital implementation of a new technique that delivers an extremely accurate and stable phase locked loop system (PLL) is presented. The new technique uses competing phase and frequency loops to incorporate an accurate local reference frequency into ...
Cantoni, A., Hill, M.T.
core +1 more source
Retrospective Grid Cells in the Medial Entorhinal Cortex Encode Past Paths During Spatial Navigation
Retrospective grid cells are identified in the medial entorhinal cortex, with spatial firing patterns that become most grid‐like when activity is projected onto recently traversed locations. Their coding loses spatial precision in darkness and is disrupted during assisted movement, indicating that entorhinal representations incorporate recent path ...
Ruojin Liu +10 more
wiley +1 more source
Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques
This article proposes an mm-wave fractional-N all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, consequently improving jitter at lower power ...
Teerachot Siriburanon +3 more
doaj +1 more source
DESIGN & IMPLEMENTATION OF FRACTIONAL – N FREQUENCY SYNTHESIZER
This research involves design & implementation of fractional – N frequency synthesizer with the following specifications: Frequency range (2350– 2750) MHz,Step size (1 kHz), Switching time 8.9 μs, & phase noise @10 kHz = -115dBc & spurious -69 dBc The ...
Ali M. N. Hassan
doaj +1 more source

