Results 21 to 30 of about 1,070 (143)
IEEE Access, 2020 In this paper, an ultra-low power, adaptive all-digital integer frequency-locked loop (FLL) with gain estimation and constant current digitally controlled oscillator (DCO) for Bluetooth low energy (BLE) transceiver in Internet-of-Things (IoT) is ...
Imran Ali +9 more
doaj +1 more source
Design of a 3 GHz fine resolution LC DCO [PDF]
, 2017 In this thesis, the design of a fine resolution LC digitally controlled oscillator (DCO) is introduced. Two NMOS varactor banks are used to achieve 12 bits medium and fine frequency tuning.
Zhao, Xuming, active 21st century
core +1 more source
A Varactor-Less DCO With
IEEE Access, 2019 The generation of precise linear frequency modulation is a critical requirement for millimeterwave automotive radars. This paper presents the analysis and design of a CMOS 75.5 - 82.5 GHz monotonically linear digitally controlled oscillator (ML-DCO ...
Iman Taha, Mitra Mirhassani
doaj +1 more source
Design of Low Power 6-bit Digitally-Controlled Oscillator (DCO)
International Journal on Electrical Engineering and Informatics, 2014 A low power 6-bit CMOS ring based digitally controlled oscillator (DCO) design is presented. The design is proposed based on binary-to-thermometer (BT) decoder current mirror digital-to-analog converter (DAC) and ring-based voltage controlled oscillator (VCO).
Mohammad Anisur Rahman +4 more
openaire +1 more source
A 2.4GHz 830pJ/bit duty-cycled wake-up receiver with −82dBm sensitivity for crystal-less wireless sensor nodes [PDF]
, 2010 A 65 nm CMOS 2.4 GHz wake-up receiver operating with low-accuracy frequency references has been realized. Robustness to frequency inaccuracy is achieved by employing non-coherent energy detection, broadband-IF heterodyne architecture and impulse-radio ...
Breems, L.J. +5 more
core +3 more sources
Architecture and Control of a Digital Frequency-Locked Loop for Fine-Grain Dynamic Voltage and Frequency Scaling in Globally Asynchronous Locally Synchronous Structures [PDF]
, 2011 International audienceA small area fast-reprogrammable Digital Frequency-Locked Loop (DFLL) engine is presented as a solution for the Dynamic Voltage and Frequency Scaling (DVFS) circuitry in Globally Asynchronous Locally Synchronous (GALS) architectures
Carolina Albea +5 more
core +4 more sources
Indoor Visible Light Communication: A Tutorial and Survey
Wireless Communications and Mobile Computing, Volume 2020, Issue 1, 2020., 2020 With the advancement of solid‐state devices for lighting, illumination is on the verge of being completely restructured. This revolution comes with numerous advantages and viable opportunities that can transform the world of wireless communications for the better.
Galefang Allycan Mapunda +6 more
wiley +1 more source
Multi-Channel Two-way Time of Flight Sensor Network Ranging [PDF]
, 2012 Two-way time of flight (ToF) ranging is one of the most interesting approaches for localization in wireless sensor networking since previous ToF ranging approaches using commercial off-the-shelf (COTS) devices have achieved good accuracy.
Eriksson, Joakim +3 more
core +2 more sources
Digital tanlock loop architecture with no delay [PDF]
, 2011 This article proposes a new architecture for a digital tanlock loop which eliminates the time-delay block. The =2 (rad) phase shift relationship between the two channels, which is generated by the delay block in the conventional timedelay digital ...
AL-Ali, Omar Al-Kharji +4 more
core +1 more source
Noise shaping Asynchronous SAR ADC based time to digital converter [PDF]
, 2018 Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits.
Katragadda, Sowmya
core +1 more source