Results 161 to 170 of about 97,626 (219)
A computationally efficient pulse compression method of Barker-coded excitation using a mismatched filter in medical ultrasound imaging. [PDF]
UltrasonographyHan M, Choi HJ, Yoon C.
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PF-DRAM: A Precharge-Free DRAM Structure
2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA), 2021Although DRAM capacity and bandwidth have increased sharply by the advances in technology and standards, its latency and energy per access have remained almost constant in recent generations. The main portion of DRAM power/energy is dissipated by Read, Write, and Refresh operations, all initiated by a Precharge phase. Precharge phase not only imposes a
Nezam Rohbani +2 more
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The Charleston Advisor, 2019
DRAM, a product of the educational foundation Anthology of Recorded Music, Inc., is a streaming audio database whose mission is to preserve and disseminate musical recordings based upon their aesthetic and historical value, which are largely ignored by the commercial marketplace.
Leanna Goodwater +2 more
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DRAM, a product of the educational foundation Anthology of Recorded Music, Inc., is a streaming audio database whose mission is to preserve and disseminate musical recordings based upon their aesthetic and historical value, which are largely ignored by the commercial marketplace.
Leanna Goodwater +2 more
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VRL-DRAM: Improving DRAM Performance via Variable Refresh Latency
2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), 2018A DRAM chip requires periodic refresh operations to prevent data loss due to charge leakage in DRAM cells. Refresh operations incur significant performance overhead as a DRAM bank/rank becomes unavailable to service access requests while being refreshed.
Anup Das, Hasan Hassan, Onur Mutlu
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Statistics and Computing, 2006
We propose to combine two quite powerful ideas that have recently appeared in the Markov chain Monte Carlo literature: adaptive Metropolis samplers and delayed rejection. The ergodicity of the resulting non-Markovian sampler is proved, and the efficiency of the combination is demonstrated with various examples.
H. HAARIO +3 more
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We propose to combine two quite powerful ideas that have recently appeared in the Markov chain Monte Carlo literature: adaptive Metropolis samplers and delayed rejection. The ergodicity of the resulting non-Markovian sampler is proved, and the efficiency of the combination is demonstrated with various examples.
H. HAARIO +3 more
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Session 23 overview: DRAM, MRAM & DRAM interfaces
2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017Dynamic memories are at the heart of every computing system. Improvements in the memory sub-system are therefore directly impacting user experience - battery-powered systems operate longer, graphics are crisper and our phones will simply react more smoothly.
Takefumi Yoshikawa +2 more
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1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1984
This paper describes the physical limits of VLSI dynamic random-access memories (dRAM's). To achieve memory capacities in the multimegabit range, the significant limits inherent in conventional dRAM technology must be identified and overcome. Limits associated with cell components may be circumvented using an approach that treats the dRAM as a ...
L.L. Lewyn, J.D. Meindl
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This paper describes the physical limits of VLSI dynamic random-access memories (dRAM's). To achieve memory capacities in the multimegabit range, the significant limits inherent in conventional dRAM technology must be identified and overcome. Limits associated with cell components may be circumvented using an approach that treats the dRAM as a ...
L.L. Lewyn, J.D. Meindl
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Which DRAM will win the great DRAM sweepstakes?
1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 1993A summary of recent DRAM (dynamic random-access memory) development is presented. DRAM architectures using different philosophies have recently emerged to fill the needs of high-performance systems. Among these are cached DRAMs (CDRAMs), Rambus DRAMs (RDRAMs), RamLink DRAMs, and synchronous DRAMs (SDRAMs).
M. Slater +6 more
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