Results 51 to 60 of about 97,626 (219)
In-Depth Review and Comparative Analysis of DRAM-Based PUFs
Dynamic Random-Access Memory Physical Unclonable Functions (DRAM PUFs) are gaining interest in hardware security, particularly for resource-constrained IoT devices such as smart sensors in the era of rapid digitalization. Since DRAM is present in most of
Yuin Yee Chew +3 more
doaj +1 more source
OS Scheduling Algorithms for Memory Intensive Workloads in Multi-socket Multi-core servers
Major chip manufacturers have all introduced multicore microprocessors. Multi-socket systems built from these processors are routinely used for running various server applications.
Durbhakula, Murthy
core +1 more source
Al:ITZO‐based capacitorless 2T0C DRAMs are realized by combining N2O plasma‐induced defect modulation with read‐transistor W/L optimization to suppress leakage and stabilize data storage. This device‐level engineering enables zero‐bias hold operation, retention times exceeding 1000 s, and a 13‐fold expansion of the memory window, demonstrating a ...
Chahwan Yang +3 more
wiley +1 more source
The Value-of-Information in Matching with Queues
We consider the problem of \emph{optimal matching with queues} in dynamic systems and investigate the value-of-information. In such systems, the operators match tasks and resources stored in queues, with the objective of maximizing the system utility of ...
Bishop C., Chung F.
core +1 more source
A Genomic Catalog of Migratory Microbiomes from Wild Birds across China's Habitats
ABSTRACT Migratory birds play an important role in the spread of antimicrobial resistance (AMR); however, gaps in surveillance data from vital regions along migratory flyways across China limit the detection of emergent threats. Here, we assembled 340 metagenomes from 52 bird species covering 11 provincial administrative districts in China, presenting ...
Yanan Wang +13 more
wiley +1 more source
A physics‐based compact model for Conductive‐Metal‐Oxide/HfOx ReRAM, accounting for ion dynamics, electronic conduction, and thermal effects, is presented. Accurate and versatile simulations of analog non‐volatile conductance modulation and memory state stabilization enable reliable circuit‐level studies, advancing the optimization of neuromorphic and ...
Matteo Galetta +9 more
wiley +1 more source
Parallelism-Aware Memory Interference Delay Analysis for COTS Multicore Systems [PDF]
In modern Commercial Off-The-Shelf (COTS) multicore systems, each core can generate many parallel memory requests at a time. The processing of these parallel requests in the DRAM controller greatly affects the memory interference delay experienced by ...
Yun, Heechul
core
This review surveys oxide‐semiconductor devices for in‐memory and neuromorphic computing, highlighting recent progress and remaining challenges in charge‐trap, ferroelectric, and two‐transistor devices. Oxide semiconductors, featuring ultra‐low leakage, low‐temperature processing, and back‐end‐of‐line compatibility, are explored for analog in‐memory ...
Suwon Seong +4 more
wiley +1 more source
DRAM scalability is becoming a limiting factor to the available memory capacity in consumer devices. As a potential solution, manufacturers have introduced emerging non-volatile memories (NVMs) into the market, which can be used to increase the memory ...
Geraldo F. Oliveira +10 more
doaj +1 more source
Tiered-latency DRAM: A low latency and low cost DRAM architecture [PDF]
The capacity and cost-per-bit of DRAM have historically scaled to satisfy the needs of increasingly large and complex computer systems. However, DRAM latency has remained almost constant, making memory latency the performance bottleneck in today's systems. We observe that the high accesslatency is not intrinsic to DRAM, but a trade-off made to decrease
Donghyuk Lee +5 more
openaire +1 more source

