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ExaFlexHH: an exascale-ready, flexible multi-FPGA library for biologically plausible brain simulations. [PDF]
Front NeuroinformMiedema R, Strydis C.
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In-Sensor-Memory Computing for Post-Von Neumann Intelligence: A Perspective. [PDF]
Nanomicro LettTang H, Yu N, Min P, Guo R, Zhang G.
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Exploiting neuro-inspired dynamic sparsity for energy-efficient intelligent perception. [PDF]
Nat CommunZhou S +4 more
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Deep Learning Based Diagnostics for Rowhammer Protection of DRAM Chips
2019 IEEE 28th Asian Test Symposium (ATS), 2019Modern day DRAM chips have been shown to have a reliability issue which can lead to erratic bit flips, a phenomenon which is called Rowhammer. Although current DRAM modules come with in-built countermeasures, recent attacks have shown they are still vulnerable. The Rowhammer vulnerability has been used in conjunction with other side-channels to lead to
Manaar Alam, Debdeep Mukhopadhyay
exaly +2 more sources
Design-Induced Latency Variation in Modern DRAM Chips
Proceedings of the ACM on Measurement and Analysis of Computing Systems, 2017 Variation has been shown to exist across the cells within a modern DRAM chip. Prior work has studied and exploited several forms of variation, such as manufacturing-process- or temperature-induced variation.
Donghyuk Lee +2 more
exaly +3 more sources
The cache DRAM architecture: a DRAM with an on-chip cache memory
IEEE Micro, 1990A DRAM (dynamic RAM) with an on-chip cache, called the cache DRAM, has been proposed and fabricated. It is a hierarchical RAM containing a 1-Mb DRAM for the main memory and an 8-kb SRAM (static RAM) for cache memory. It uses a 1.2- mu m CMOS technology.
Hideto Hidaka +3 more
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A customized design of DRAM controller for on-chip 3D DRAM stacking
IEEE Custom Integrated Circuits Conference 2010, 2010To address the “memory wall” challenge, on-chip memory stacking has been proposed as a promising solution. The stacking memory adopts three-dimensional (3D) IC technology, which leverages through-silicon-vias (TSVs) to connect layers, to dramatically reduce the access latency and improve the bandwidth without the constraint of I/O pins.
Tao Zhang 0032 +7 more
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IEEE Journal of Solid-State Circuits, 1995
DRAM macros in 4-Mb (0.8-/spl mu/m) and 16-Mb (0.5-/spl mu/m) DRAM process technology generations have been developed for CMOS ASIC applications. The macros use the same area efficient one transistor trench cells as 4-Mb (SPT cell) and 16-R Mb (MINT cell) DRAM products.
T. Sunaga +8 more
openaire +1 more source
DRAM macros in 4-Mb (0.8-/spl mu/m) and 16-Mb (0.5-/spl mu/m) DRAM process technology generations have been developed for CMOS ASIC applications. The macros use the same area efficient one transistor trench cells as 4-Mb (SPT cell) and 16-R Mb (MINT cell) DRAM products.
T. Sunaga +8 more
openaire +1 more source