Results 141 to 150 of about 941 (185)

Skinflint DRAM system: Minimizing DRAM chip writes for low power

2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), 2013
DRAMs are one of the main players of computer system energy consumption due to their large capacities and frequent accesses. Consequently, many schemes have been proposed to reduce DRAM power/energy consumption. Some of them propose new DRAM system and chip organizations, which are effective in reducing power consumption but intrusive.
Yebin Lee, Soontae Kim, Seokin Hong, Jongmin Lee 0002   +3 more
openaire   +1 more source

A parallel processing chip with embedded DRAM macros

IEEE Journal of Solid-State Circuits, 1996
A combined DRAM and logic chip has been developed for massively parallel processing (MPP) applications. A trench cell 4-Mb CMOS DRAM technology is used to fabricate the chip with an additional third-level metal layer. The 5-V 0.8-/spl mu/m technology merges 100-K gate custom logic circuits and 4.5-Mb DRAM onto a 14.7/spl times/14.7 mm/sup 2/ die.
Toshio Sunaga, Hisatada Miyatake, Koji Kitamura, Peter M. Kogge, Eric Retter   +4 more
openaire   +1 more source

Limitations and challenges of multigigabit DRAM chip design

IEEE Journal of Solid-State Circuits, 1997
This paper describes the limitations and challenges involved in designing gigabit DRAM chips in terms of high-density devices, high-performance circuits, and low-power/low-voltage circuits. The key results obtained are as follows. 1) For formation of a MOSFET shallow junction, which suppresses threshold voltage (V/sub T/) variation and offset voltage ...
Kiyoo Itoh 0001, Yoshinobu Nakagome, Shin'ichiro Kimura, Takao Watanabe   +3 more
openaire   +1 more source

An embedded DRAM-FPGA chip with instantaneous logic reconfiguration

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251), 1997
Reconfigurable computing is attracting wide attention as a novel general purpose computing paradigm for accelerating compute intensive and/or data-parallel applications, such as compression, encryption, searching, sorting, and image processing. A key enabling technology for a reconfigurable computer is in-system logic reconfiguration of SRAM-based ...
Masato Motomura, Yoshiharu Aimoto, Atsufkni Shibayama, Yoshikazu Yabe, Masakazu Yamashina   +4 more
openaire   +1 more source

Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis

Processing-using-DRAM (PuD) is an emerging paradigm that leverages the analog operational properties of DRAM circuitry to enable massively parallel in-DRAM computation.
Ismail Emir Yuksel, Yahya Can Tugrul, Ataberk Olgun   +2 more
exaly   +2 more sources

A CMOS DRAM controller chip implementation

IEEE Journal of Solid-State Circuits, 1987
A DRAM controller which handles up to 128 1-Mb DRAM chips has been developed based on the WE 32100 32-bit microsystem. Fabricated with a 1.5 /spl mu/m twin-tub CMOS technology, nominal DRC devices operate at an internal clock rate of 36 MHz. High circuit speed was achieved by the use of clock-skew minimization techniques to limit clock signal ...
T.C. Poon, M. Kerestes, R.F. Fischer, G.P. Sampson, S. Hwang, W.J. Yang, M.L. Willis   +6 more
openaire   +1 more source

Development of chip scale package for DRAM

Twenty Fourth IEEE/CPMT International Electronics Manufacturing Technology Symposium (Cat. No.99CH36330), 2003
In order to assemble a chip scale package (CSP), a die with centralized bonding pads was mounted on a printed circuit board (PCB) using adhesive film, and was wire-bonded through a slot formed along the PCB center area, followed by encapsulation. After solder ball attachment, a PCB strip was divided into individual packages by punching.
T.J. Cho, E.C. Ahn, J.H. Lyu, M.G. Chung, S.Y. Oh   +4 more
openaire   +1 more source

A prototype chip of multicontext FPGA with DRAM for virtual hardware

Proceedings of the 2001 conference on Asia South Pacific design automation - ASP-DAC '01, 2001
DRAM-type multicontext FPGA has potential for virtual hardware, since it is possible to implement a large number of contexts in a single chip. However, only a few examples have been reported because of the difficulty of the mixed process involving DRAM and logic. Here we try to implement a prototype multicontext FPGA with DRAM for virtual hardware.
Daisuke Kawakami, Yuichiro Shibata, Hideharu Amano   +2 more
openaire   +1 more source

Distributed fair DRAM scheduling in network-on-chips architecture

Journal of Systems Architecture, 2013
Memory access scheduling is an effective manner to improve performance of Chip Multi-Processors (CMPs) by taking advantage of the timing characteristics of a DRAM. A memory access scheduler can subdivide resources utilization (banks and rows) to increase throughput by accessing different DRAM banks in parallel.
Masoud Dehyadegari, Siamak Mohammadi, Nasser Yazdani   +2 more
openaire   +1 more source

Understanding RowHammer Under Reduced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions

Ergin, Oguz/0000-0003-2701-3787Read disturbance in modern DRAM chips is a widespread weakness that is used for breaking memory isolation, one of the fundamental building blocks of system security and privacy.
Yahya Can Tugrul, Ismail Emir Yuksel, Ataberk Olgun   +2 more
exaly   +2 more sources