Results 151 to 160 of about 941 (185)
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Combined DRAM and logic chip for massively parallel systems
Proceedings Sixteenth Conference on Advanced Research in VLSI, 2002A new 5 V 0.8 /spl mu/m CMOS technology merges 100 K custom circuits and 4.5 Mb DRAM onto a single die that supports both high density memory and significant computing logic. One of the first chips built with this technology implements a unique Processor-In-Memory (PIM) computer architecture termed EXECUBE and has 8 separate 25 MHz CPU macros and 16 ...
Peter M. Kogge +4 more
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We experimentally analyze the computational capability of commercial off-the-shelf (COTS) DRAM chips and the robustness of these capabilities under various timing delays between DRAM commands, data patterns, temperature, and voltage levels.
Ismail Emir Yuksel
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An experimental 1Mb DRAM with on-chip voltage limiter
1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1984This paper will report on an experimental 21μm2cell, single 5V 1Mb NMOS DRAM. Typical clata are: access time 90ns, power dissipation 300mW at 260ns cycle time.
K. Itoh +6 more
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Embedding DRAM in single chip MPEG1 codec LSI
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327), 2003We have successfully designed the low power single chip MPEG1 codec LSI which is the most suitable for portable devices such as digital cameras. By adopting compact and efficient motion estimation process and embedding SDRAM for storing image data inside, this chip realizes compactness and low power of the system.
T. Fujihira +3 more
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An Experimental Study on Dynamic Bank Partitioning of DRAM in Chip Multiprocessors
2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), 2017Concurrent execution of multiple applications on chip multiprocessors leads to interference at different level of shared resources like the banks of a DRAM. There are a few studies in literature suggest that we can dynamically partition the DRAM banks among the running processes.
Debiprasanna Sahoo +2 more
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A novel on-chip voltage generator for low voltage DRAMs and PRAMs
2009 IEEE Custom Integrated Circuits Conference, 2009A novel on-chip voltage generator suitable for low voltage operation has been developed and demonstrated through a 128Mb PRAM test chip using 72nm CMOS process. It features three key circuit techniques as follows: 1) a cross charge pump circuit with a shift charge method , which generates VPP supply current larger over 35% than conventional pump ...
Tatsuya Matano +3 more
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Development of a high bandwidth merged logic/DRAM multimedia chip
Proceedings International Conference on Computer Design VLSI in Computers and Processors, 1997This paper describes the design methodology and the implementation of a merged logic/DRAM multimedia chip. The design is based on 0.25 micron DRAM-based CMOS technology with 4-layers of metal with device performance enhancement. Details of the architecture and system design of the multi-media was described in Katayama et. al. (1996).
W. K. Luk +10 more
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DRAM read disturbance can break memory isolation, a fundamental property to ensure system robustness (i.e., reliability, security, safety). RowHammer and RowPress are two different DRAM read disturbance phenomena. RowHammer induces bitflips in physically
Haocong Luo +2 more
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Rethinking on-chip DRAM cache for simultaneous performance and energy optimization
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017State-of-the-art DRAM cache employs a small Tag-Cache and its performance is dependent upon two important parameters namely bank-level-parallelism and Tag-Cache hit rate. These parameters depend upon the row buffer organization. Recently, it has been shown that a small row buffer organization delivers better performance via improved bank-level ...
Fazal Hameed, Jerónimo Castrillón
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Embedded DRAM: Technology platform for the Blue Gene/L chip
IBM Journal of Research and Development, 2005The Blue Gene®/L chip is a technological tour de force that embodies the system-on-a-chip concept in its entirety. This paper outlines the salient features of this 130-nm complementary metal oxide semiconductor (CMOS) technology, including the IBM unique embedded dynamic random access memory (DRAM) technology. Crucial to the execution of Blue Gene/L is
Subramanian S. Iyer +6 more
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