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An on-chip ECC circuit for correcting soft errors in DRAMs with trench capacitors
IEEE Journal of Solid-State Circuits, 1992A modified error-correcting code that can correct up to two soft errors on each row (word line) in a dynamic random-access memory (DRAM) chip is proposed. Double-bit soft errors frequently occur in DRAM cells with trench capacitors, when charged alpha particles impinge on the intervening space between two vertical capacitors causing plasma shorts ...
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Design of a Fault-Tolerant DRAM with New On-Chip ECC
1989Soft errors induced by incident alpha particles are one of the most serious problems at present and in future VLSI dynamic random-access memory (DRAM) development. Alpha particles emitted during radioactive decay of uranium and thorium, contained in minute proportions in packaging materials [1], have been shown to cause 98% failures that occur during ...
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Cosmic ray soft error rates of 16-Mb DRAM memory chips
IEEE Journal of Solid-State Circuits, 1998J F Ziegler
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HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips
2022Ataberk Olgun +2 more
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A Mechanism for Dependence of Refresh Time on Data Pattern in DRAM
IEEE Electron Device Letters, 2010Myoung Jin Lee
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On-Chip Decoupling Capacitor Placement with Impedance Constraint for DRAM Design
2025 ACM/IEEE 7th Symposium on Machine Learning for CAD (MLCAD)Minseung Shin +3 more
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DRAM Refresh Mechanisms, Penalties, and Trade-Offs
IEEE Transactions on Computers, 2016Zeshan Chishti +2 more
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Reducing DRAM Latency by Exploiting Design-Induced Latency Variation in Modern DRAM Chips.
CoRR, 2016Donghyuk Lee +7 more
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