Results 161 to 170 of about 941 (185)

Using cache mechanisms to exploit nonrefreshing DRAMs for on-chip memories

IEEE Journal of Solid-State Circuits, 1991
On-chip memories are becoming an established feature in single-chip microprocessor designs because they significantly improve performance. It is particularly important for single-chip reduced instruction set computer (RISC) microprocessors to include large, high-speed memories, because RISC chips must reduce off-chip memory delays to achieve the ...
David D. Lee, Randy H. Katz
openaire   +1 more source

Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM

2015 IEEE International Reliability Physics Symposium, 2015
Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip were evaluated. The retention characteristics of memory cells were degraded depending on the decreased chip thickness, especially dramatically degraded below 40-μm thickness in the case with under-fill, meanwhile, the retention characteristics were relatively not so ...
Kang Wook Lee 0002, Ji Chel Bea, Mariappan Murugesan, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi   +5 more
openaire   +1 more source

Read Disturbance in High Bandwidth Memory: A Detailed Experimental Study on HBM2 DRAM Chips

We experimentally demonstrate the effects of read disturbance (RowHammer and RowPress) and uncover the inner workings of undocumented read disturbance defense mechanisms in High Bandwidth Memory (HBM).
Ataberk Olgun, Yahya Can Tugrul, Haocong Luo   +2 more
exaly   +2 more sources

A new on-chip converter for submicrometer high-density DRAMs

IEEE Journal of Solid-State Circuits, 1987
The converter described is a feedback-type voltage regulator which supplies a reduced voltage to an entire RAM circuit. A novel timing activation method was introduced to save power. The converter has been implemented on an experimental 4-Mb dynamic RAM.
T. Furuyama, Y. Watanabe, T. Ohsawa, S. Watanabe   +3 more
openaire   +1 more source

INTEGRATED DRAM MEMORY CHIP

2003
The invention relates to an integrated DRAM memory chip comprising sense amplifiers, each configured for the integrated module from a large number of transistor structures and signal conduction pathway structures that are arranged in a regular pattern in cell fields.
INFINEON TECHNOLOGIES AG, CHRYSOSTOMIDES ATHANASIA, SZCZYPINSKI KAZIMIERZ, FISCHER HELMUT   +3 more
openaire   +1 more source

Development of single-chip multi-GB/s DRAMs

1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers, 2002
Discusses improvement of current device jitter budget. A DRAM incorporating these improvements is expected to operate with 1.3Gb/s/pin signaling rate (650MHz clock rate) delivering 5.2GB/s from a 32b interface. Such a 64Mb density DRAM will exhibit a fill rate of 650times/s. Compared to an industry-standard 64M SDRAM operating at 66MHz with its 33times/
R. Crisp, K. Donnelly, A. Moncayo, D. Perino, J. Zerbe   +4 more
openaire   +1 more source

Flexible-Latency Dram: Understanding and Exploiting Latency Variation in Modern Dram Chips

2021
This article summarizes key results of our work on experimental characterization and analysis of latency variation and latency-reliability trade-offs in modern DRAM chips, which was published in SIGMETRICS 2016 [ 24], and examines the work's signifficance and future potential.
Chang, Kevin K., Ghose, Saugata, Hsieh, Kevin, Lee, Donghyuk, Mutlu, Onur, Kashyap, Abhijith, Hassan, Hasan   +6 more
openaire   +1 more source

Asymmetric DRAM synthesis for heterogeneous chip multiprocessors in 3D-stacked architecture

Proceedings of the International Conference on Computer-Aided Design, 2012
Various computational requirements of real-world applications have leveraged moving to heterogeneous chip multiprocessors (CMPs) from homogeneous ones. In the meantime, three-dimensional integration of DRAMs and processors using Through Silicon Vias (TSVs) has emerged as the most viable solution for breaking the memory wall in CMP environment by ...
Minje Jun, Myoung-Jin Kim, Eui-Young Chung   +2 more
openaire   +1 more source

A Self-Authenticating Chip Architecture Using an Intrinsic Fingerprint of Embedded DRAM

IEEE Journal of Solid-State Circuits, 2013
An architecture for enabling self-authenticating chips uses 4 Kb electrically programmable fuses (eFUSE) to store bit strings representing encrypted intrinsic fingerprints obtained by offset-superimposing six out of one thousand 4 Kb domains randomly chosen in 4 Mb embedded DRAM.
Sami Rosenblatt, Srivatsan Chellappa, Alberto Cestero, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer   +5 more
openaire   +1 more source

Polyimide fatigue induced chip surface damage in DRAM's Lead-On-Chip (LOC) packages

33rd IEEE International Reliability Physics Symposium, 1995
The effect of mechanical fatigue on reliability failure was studied, based on plastic fracture mechanics including stress intensity factor, stress singularity, micro-plastic deformation behavior, and stress-strain characteristics. The fatigue has made the mechanical stability of novel lead-on-chip (LOC) packaging technologies a grave concern.
openaire   +2 more sources