Results 11 to 20 of about 381 (171)
Correction Masking: a technique to implement efficient SET tolerant error correction decoders [PDF]
, 2022 Single Event Transients (SETs) can be a major concern for combinational circuits. Its importance grows as technology scales because a small charge can create a large disturbance on a circuit node.
Liu, He +3 more
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Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial
Sensors, 2021 Communication systems that work in jeopardized environments such as space are affected by soft errors that can cause malfunctions in the behavior of the circuits such as, for example, single event upsets (SEUs) or multiple bit upsets (MBUs).
Óscar Ruano +5 more
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Codes for Limited Magnitude Error Correction in Multilevel Cell Memories [PDF]
, 2020 Multilevel cell (MLC) memories have been advocated for increasing density at low cost in next generation memories. However, the feature of several bits in a cell reduces the distance between levels; this reduced margin makes such memories more vulnerable
Shanshan, Liu +2 more
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IEEE Access, 2020 As a class of convolutional error-correction codes (ECCs), spatially coupled protograph low-density parity-check (SC-PLDPC) codes with a sufficiently large coupling length can approach the channel capacity under belief propagation (BP) decoding. However,
Yunlong Zhao, Yi Fang, Zhaojie Yang
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IEEE Access, 2023 In non-volatile random-access memory (RAM) technologies, the spin-torque transfer magnetic random-access memory (STT-MRAM) is a promising candidate. STT-MRAM has attracted attention owing to its advantages, such as a high density, high endurance, and ...
Thien An Nguyen, Jaejin Lee
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Energy-conscious turbo decoder design: a joint signal processing and transmit energy reduction approach [PDF]
, 2013 Conventionally, the decoding energy consumption Epr of turbo codes were not a significant contribution to the overall energy consumption of a system, since the popular applications of turbo codes were focused on long-range communication systems, such as ...
Maunder, R.G. +4 more
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ACM Transactions on Architecture and Code Optimization, 2016 This article proposes a rate-adaptive, two-tiered error-correction scheme (RATT-ECC) that provides strong reliability (10 10 x reduction in raw FIT rate) for an HBM-like 3D DRAM system.
Hsing Min Chen +3 more
openaire +1 more source
Error-Resilient Data Compression With Tunstall Codes [PDF]
, 2023 Data compression has been commonly employed to reduce the required memory size for emerging applications with large storage needs like Big Data and Machine Learning (ML).
Ullah, Anees +4 more
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Two bit overlap: a class of double error correction one step majority logic decodable codes [PDF]
, 2019 Error Correction Codes (ECCs) are commonly used to protect memories against soft errors with an impact on memory area and delay. For large memories, the area overhead is mostly due to the additional cells needed to store the parity check bits.
Rottenstreich, Ori +3 more
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Variable-Node-Based Belief-Propagation Decoding With Message Pre-Processing for NAND Flash Memory
IEEE Access, 2019 With the fast development of non-volatile storage technology, NAND flash memory faces more and more challenges such as data reliability and lifetime. To overcome the issue of the reliability, low-density parity-check (LDPC) codes are considered as a main
Xingcheng Liu, Guojun Yang, Xuechen Chen
doaj +1 more source